Radiawave Technologies Co., Ltd.

Other

Hon Hai Precision Industry Co., Ltd.

Huawei Technologies Co., Limited

Tencent Technology (shenzhen) Company Limited

Hong-fu Jin Precision Industry (shenzhen) Co., Ltd.

Bose Corporation

Ademco Inc.

Aac Technologies Pte. Ltd.

Honor Device Co., Ltd.

Shenzhen University

Ning Zhang

Jon Sweat Duster

Haigang Feng

Yulin Tan

Xiaofeng Guo

Erkan Alpman

Chiang-Kuo Tang

Jun Yang

Seth N Green

Han-Yu Li

Haidong Xu

Guobin Xu

Kuan-Hong Hsieh

Wei Xiong

Feng Xing

Ying Zhao

Chenlong Li

Hui Wen

Yigao Shao

Li-Zhang Huang

Xiaodong Wang

Haowen Xu

Ning Dong

Xin Zhu

Zhonghui Yao

Liang Kang

Jiangwei Liu

Liuan Zhang

Dawang Li

Biao Liu

Zhu Ding

Guang-Dong He

Chao Yao

Sheng-Ping Xie

Ningxu Han

Weilun Wang

Bertrand Clerc

Yuguo Liu

Wujian Long

Biqin Dong

Shuting Zhong

Yun-Quan Tang

Xiaolin Wang

Fang Qian

Xuanjiao Li

Defeng Liu

Haitong Yu

Jirong Zhou

Zhongying Huang

Xiaolan Peng

Mengqing Wu

Jinzhou Jiang

Po-Fu Cheng

Yuelong Teng

Zhenxing Zhou

Disclosed are a two-stage audio gain circuit based on analog-to-digital conversion and an audio terminal. The two-stage audio gain circuit includes a PGA configured to receive an analog audio signal and perform programmable gain amplification processing on the received analog audio signal; an ADC configured to convert the analog audio signal after the programmable gain amplification processing into a digital audio signal and output the digital audio signal; a first AGC gain unit configured to perform a first AGC processing on the digital audio signal and output a first gain adjustment value to the PGA, for the PGA to perform gain adjustment on the received analog audio signal; and a second AGC gain unit configured to perform a second AGC processing on the digital audio signal and output a second gain adjustment value to the PGA, for the PGA to perform gain adjustment on the received analog audio signal.

Two-stage audio gain circuit based on analog-to-digital conversion and audio terminal

Disclosed are an audio ADC for supporting voice wake-up and an electronic device. The audio ADC includes a programmable gain amplifier (PGA) having an input terminal for receiving an audio signal; a bypass switch having an input terminal for receiving an analog audio signal; and a successive approximation ADC having input terminals respectively connected to output terminals of the PGA and the bypass switch; the PGA gains and amplifies the audio signal, the bypass switch bypasses the PGA, and outputs the analog audio signal; the successive approximation performs analog-to-digital conversion with noise shaping on the analog audio signal after gain amplification at a first sampling rate/oversampling rate when the audio ADC is normal working, and turns off noise shaping when the audio ADC is sleep, performs analog-to-digital conversion on the analog audio signal output by the bypass switch at a second sampling rate/oversampling rate, and outputs to a DSP.

Audio ADC for supporting voice wake-up and electronic device

Disclosed are a pre-drive module of an analog-to-digital converter and an analog-to-digital conversion device. The pre-drive module includes a sampling capacitor; a controller configured to output a reset control signal, a pre-sampling control signal, and a sampling control signal according to a preset timing sequence; a reset module configured to reset the sampling capacitor upon receiving the reset control signal; a first auxiliary drive circuit configured to amplify an input analog signal and output to the sampling capacitor for sampling upon receiving the sample control signal; and a second auxiliary drive circuit. The controller is configured to output the pre-sampling control signal before outputting the sampling control signal, control the second auxiliary drive circuit to amplify the input analog signal, and output to the sampling capacitor for pre-sampling, and when a charging voltage of the sampling capacitor during pre-sampling reaches a preset voltage value, output the sampling control signal.

Pre-drive module of analog-to-digital converter, and analog-to-digital conversion device

Disclosed are an analog-to-digital converter error shaping circuit and a successive approximation analog-to-digital converter. The analog-to-digital converter error shaping circuit includes a decentralized capacitor array, a data weighted average module, a mismatch error shaping module, a control logic generation circuit, a digital filter and a decimator. The decentralized capacitor array includes two symmetrically arranged capacitor array units, each capacitor array unit includes a first sub-capacitor array of a high segment bit and a second sub-capacitor array of a low segment bit. The data weighted average module is configured to eliminate correlation between the first sub-capacitor array and an input signal, and the mismatch error shaping module is configured to eliminate correlation between the second sub-capacitor array and the input signal.

Analog-to-digital converter error shaping circuit and successive approximation analog-to-digital converter

A wireless headset includes a first headset part and a second headset part. The first headset part includes a first earplug, a battery box, and a first part of a cable control box. The first part of the cable control box includes a first interface, a first wireless chip configured to receive and send a wireless signal, and a processor configured to process the wireless signal. The battery box includes a first battery. The second headset part includes a second earplug and a second part of the cable control box, and the second part of the cable control box includes a second interface. The first interface is detachably connected to the second interface. When the first interface is electrically connected to the second interface, a data path is formed between the second earplug and the processor, and the first battery supplies power to the second earplug.

Wireless headset

A method for automatically splitting row-based table content into columns is provided, including: receiving first table content sent by a client, the first table content including one or more rows of text data to be split into columns; performing information extraction on the one or more rows of text data in the first table content to obtain an information tag in the one or more rows of text data; performing column splitting on the one or more rows of text data according to the information tag to obtain second table content, the second table content comprising one or more columns of text data after the column splitting; and transmitting the second table content to the client.

Method and apparatus for automatically splitting table content into columns, computer device, and storage medium

A reference voltage controlling circuit and an analog-to-digital converter are disclosed. The reference voltage controlling circuit includes a reference voltage generating circuit, a plurality of groups of sampling switching units and a logic controlling circuit. The DAC capacitor array switches the sampling switching units to a second positive reference voltage and a second negative reference voltage before starting sampling or conversion, and is charged and discharged with the second positive reference voltage and the second negative reference voltage to raise a voltage to a preset voltage. The sampling switching unit is switched to a first positive reference voltage and a first negative reference voltage to charge and discharge the DAC capacitor array to a target voltage. The rising of the voltage from the preset voltage to the target voltage is completed by the first positive reference voltage and the first negative reference voltage.

Reference voltage controlling circuit and analog-to-digital converter

The present disclosure provides a manufacturing method of a TFT pattern, and a mask, which is used to make light pass through a hole corresponding to a position of the TFTs on the mask which is disposed on the TFTs, thereby producing two or more stacked photoresists on the TFTs to counteract a reflected light on a semiconductor As layer and ensure normal working of the TFTs.

Manufacturing method of thin film transistor pattern using different color masks and multilayer photoresists, thin film transistor, and mask thereof

A residue transfer loop, a successive approximation register analog-to-digital converter and a gain calibration method are disclosed. In particular, the residue transfer loop includes a sampling switch module, a logic controlling circuit, a residue holding capacitor module, a DAC capacitor array, a residue transfer module, a current rudder, a reset switch module and a charge sharing switch module. The logic controlling circuit sequentially outputs control signals according to preset time intervals in a preset period to control the reset switch module, the residue transfer module, the sampling switch module and the charge sharing switch module to work sequentially, thereby realizing a residue transfer.

Residue transfer loop, successive approximation register analog-to-digital converter, and gain calibration method

The present disclosure provides a power amplifier and an electrical device. The two-stage power amplifier architecture is tuned staggered before power combining. A previous stage matching network and its input matching are split into a cascaded staggered tuning, such that the center frequency is at frequency pointless than the design frequency point and frequency pointgreater than design frequency point, and then the power combining stage is tuned at the design frequency point. At advanced process nodes (such as 65 nm or below), compared with the known architecture, in-band signal quality and out-of-band filtering effect of the power amplifier chip integrating this architecture will be better when using the same number of transformers (same area), the reliability will be better. Due to its good flatness within the band, this architecture is especially suitable for carrier aggregation communication occasions.

Power amplifier and electronic device

The present application discloses an N-bit hybrid-structure analog-to-digital converter and an integrated circuit chip including the same, including a pre-stage sampling capacitor array, a post-stage capacitor array and a comparator set and the pre-stage sampling capacitor array including a number of 2&#x2212;1 sets of first capacitor array units arranged in parallel, the first capacitor array unit including two sets of parallel capacitor strings, input terminals of parallel capacitor strings respectively being connected to and switchable between differential analog signals and first preset reference signals, output terminals of the parallel capacitor strings respectively being connected to input terminals of the comparator set, input terminals of the post-stage capacitor array respectively being connected to and switchable between output terminals of the comparator set and differential analog signals, output terminals of the post-stage capacitor array being configured as an output terminal of the analog-to-digital converter.

N-bit hybrid structure analog-to-digital converter and integrated circuit chip including the same

The present disclosure provides a dual-edge triggered ring buffer and a communication system. The dual-edge triggered ring buffer includes a logic clock generation module and a data writing module. The logic clock generation module is configured to generate a corresponding first logic clock signal upon detecting an input of the trigger signal corresponding to the multiple first trigger signal input terminals, or to generate a corresponding second logic clock signal upon detecting an input of the trigger signal corresponding to the multiple second trigger signal input terminals. The data writing module is configured to write data output from the external system through the multiple corresponding input terminals according to the first logic clock signal or the second logic clock signal.

Dual-edge triggered ring buffer and communication system

The present disclosure relates to a capacitor array for an analog-to-digital converter, a successive approximation register analog-to-digital converter and a capacitor array board. The capacitor array includes a control logic generation circuit, a control code logic conversion circuit, a first sub-capacitor array and a second sub-capacitor array configured to form different regions of a high-order bit region and a low-order bit region. In the present disclosure, the capacitances of the second capacitor units are equal, so that the second capacitor units can be sequentially switched. Thus, no matter which bit in the second binary code changes, it will not cause a large number of the second capacitor units to switch together, thereby reducing conversion error. In addition, the capacitor array is divided in regions, which avoids the problem of a large number of parallel branches in case where only the second sub-capacitor array is arranged.

Capacitor array, successive approximation register analog-to-digital converter and capacitor array board

The present disclosure relates to a mismatch calibration circuit for a current steering DAC of a SoC baseband chip and a SoC baseband chip. The mismatch calibration circuit includes current mirror compensation circuits, a calibration switching switch module, a calibration resistor, a voltage detection module, and a calibration control module. The resistance of the calibration resistor is 2&#x2212;1 times the resistance of the load resistor, where N is the number of MSBs. The number of the current mirror compensation circuits is equal to the number of the MSB current mirror branches. The current mirror compensation circuits are connected in parallel with the MSB current mirror branches to form current mirror parallel branches. The present disclosure minimizes mismatch error between the output currents of the current mirror array in the SoC baseband chip of 28 nm process or even a smaller process dimension, thereby improving conversion accuracy of the DAC.

SOC baseband chip and mismatch calibration circuit for a current steering digital-to-analog converter thereof

The present disclosure provides an acoustic device. A vibrating diaphragm includes an edge and a damper for fixing and supporting the edge, where the damper includes a middle dome and a circuit board for fixing and supporting the middle dome, the fixing part of the circuit board is provided with a conductive part electrically connected to a voice coil lead; and an orthographic projection of the middle dome on the circuit board is not overlapped with the conductive part. The orthographic projection of the middle dome of the acoustic device on the circuit board is not overlapped with the conductive part during spot welding between the circuit board and the voice coil, therefore the problem of a short circuit of an aluminum foil dome caused by the fact that the circuit board is broken down due to overhigh spot welding temperature and pressure can be avoided.

Acoustic device

Growing community of inventors

Shenzhen, China

Ning Zhang