Gowin Semiconductor Corporation

Other

Ning Song

Jinghui Zhu

Jianhua Liu

Chienkuang Chen

Diwakar Chopperla

Xiaozhi Lin

Tianping Wang

Zhenyu Gu

Tianxin Wang

San-Ta Kow

Tun Jun Gao

A configurable semiconductor device ('CSD') is organized in four (4) quadrants able to perform user-defined logic functions via a clock fabric. The first quadrant, in one embodiment, includes a first serializer and deserializer (“SerDes”) region and a bank0 region for data processing. The second quadrant includes a second SerDes region and a bank5 region and the third quadrant contains a bank3 region and a bank4 region. The fourth quadrant includes a bank1 region and a bank2 region. The clock fabric is configured to provide a set of programmable or selectable clock signals with different clock speeds to various regions within the CSD.

Method and system for organizing programmable semiconductor device into multiple clock regions

A configurable semiconductor device ('CSD') is organized in four (4) quadrants able to perform user-defined logic functions via a clock fabric. The first quadrant, in one embodiment, includes a first serializer and deserializer ('SerDes') region and a bank0 region for data processing. The second quadrant includes a second SerDes region and a bank5 region and the third quadrant contains a bank3 region and a bank4 region. The fourth quadrant includes a bank1 region and a bank2 region. The clock fabric is configured to provide a set of programmable or selectable clock signals with different clock speeds to various regions within the CSD.

Methods and apparatus for organizing a programmable semiconductor device into multiple clock regions

A field-programmable gate array ('FPGA') contains a configurable semiconductor organized in multiple clock regions with a clock fabric for facilitating user-defined logic functions. The clock fabric provides a set of regional clock signals ('RCSs') generated from a clock source with a high clock signal quality (&#x201c;CSQ&#x201d;) for clocking logic blocks in a clock region. Also, a set of neighboring clock signals (&#x201c;NCSs&#x201d;) or inter-regional clock signals are generated from a neighboring clock source(s) for clocking logic blocks in two neighboring regions. In addition, the clock fabric is operable to provide secondary clock signals (&#x201c;SCSs&#x201d;) generated from the RCSs with a low CSQ for clocking logic blocks with less time-sensitive logic operations.

Methods and apparatus for providing a clock fabric for an FPGA organized in multiple clock regions

The present application discloses a system level integrated circuit chip, comprising a fixed logic module and a Programmable Logic Module; the fixed logic module comprising a CPU module, a non-volatile memory module, a high speed data transmission module, an analogue-to-digital and/or digital-to-analogue conversion module; the Programmable Logic Module comprising a user-defined field programmable gate array and a programmable control module; the CPU module is interconnected with the user-defined field programmable gate array and the programmable control module; the non-volatile memory is interconnected with the user-defined field programmable gate array and the programmable control module; the analogue-to-digital and/or digital-to-analogue conversion module are connected with the user-defined field programmable gate array; and the high speed data transmission module is interconnected with the user-defined field programmable gate array. The present application solves the problem of the combination of a variety of different devices and the integration of processing capabilities with different applications.

System level integrated circuit chip

A process or method for facilitating configuring a field programmable gate array ('FPGA') using a group of configurable logic blocks ('CLBs') to perform one or more logic functions is disclosed. The process, in one aspect, is able to designate a first region of FPGA to a dynamic power region (&#x201c;DPR&#x201d;) in accordance with a user selection for power conservation. After receiving, from a user, a first submodule with a designation of DPR, the first region of FPGA is assigned to the first logic operation. Upon setting a first primitive associated to the first region of FPGA for controlling power consumption of the DPR, a first enabling logic is created in a second region of FPGA for facilitating power management to the first submodule in the first region of FPGA via the first primitive.

Method and system for providing regional electrical grid for power conservation in a programmable device

A programmable semiconductor device capable of being selectively programmed to perform one or more logic functions includes a first region, second region, first regional power control ('RPC'), and second-to-first power control connection. The first region, in one embodiment, contains first configurable logic blocks ('CLBs') able to be selectively programmed to perform a first logic function. The second region includes a group of second CLBs configured to be selectively programmed to perform a second logic function. The first RPC port or inter-chip port which is coupled between the first and second regions facilitates dynamic power supply to the first region in response to the data in the second region. The second-to-first power control connection is used to allow the second region to facilitate and/or control power to the first region.

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Cupertino, CA, United States of America

Ning Song