Hgst Netherlands, B.v.

Alpha and Omega Semiconductor (cayman) Ltd.

Western Digital Technologies, Inc.

Hitachi Global Storage Technologies Netherlands B.v.

International Business Machines Corporation

Shocking Technologies, Inc.

Ning Shi

Shekar Mallikarjunaswamy

Brian Rodrick York

Sue Siyang Zhang

Alexander Michael Zeltser

Quang Le

Cherngye Hwang

Wen-Chien David Hsiao

Edward Hin Pong Lee

Suping Song

Yinshi Liu

Eun K Row

Vladimir Nikitin

Ming Jiang

Aron Pentek

Stefan Maat

Yi Zheng

Yimin Hsu

Hung-Chin Guthrie

Hongquan Jiang

Quan-chiu Harry Lam

Susumu Okamura

Elizabeth Ann Brinkman

Prabodh Ratnaparkhi

Robert J Fleming

Jui-lung Li

Lex Alan Kosowsky

Donald Giles Allen

Xinjiang Shen

Hicham Moulay Sougrati

Hieu Lam

Kyusik Shin

Chang-Man Park

Qi-Fan Xiao

Eric Wayne Flint

Shin Funada

Thomas L Leong

Xiaoyu Xu

Yunxiao Gao

Eric (Yongjian) Sun

Detlef Gador

April D Hixson-Goldsmith

Paul Alejon Fontejon, Jr

Aspects of the present disclosure generally relate to magnetic recording heads (such as write heads of data storage devices) that include multilayer structures to facilitate targeted switching and relatively low coercivity. In one or more embodiments, a magnetic recording head includes an iron-cobalt (FeCo) layer having a crystalline structure that is a cubic lattice structure, a first crystalline layer formed of a first material, and a second crystalline layer between the first crystalline layer and the FeCo layer. The second crystalline layer is formed of a second material different from the first material, and the second crystalline layer interfaces both the FeCo layer and the first crystalline layer. The crystalline structure of the FeCo layer has a texture of <100>.

Multilayer structures for magnetic recording devices to facilitate targeted magnetic switching and low coercivity

A bidirectional transient voltage suppressor (TVS) protection circuit includes two sets of steering diodes with a clamp device merged with a steering diode in each set. In one embodiment, the protection circuit includes a first high-side diode integrated with a first silicon controlled rectifier (SCR), a first low-side diode, a second high-side diode integrated with a second SCR, and a second low-side diode. In another embodiment, the protection circuit includes a first high-side diode, a first low-side diode integrated with a first SCR, a second high-side diode, and a second low-side diode integrated with a second SCR. In some embodiments, the TVS protection circuit realizes low capacitance at the protected nodes by fully or almost completely depleting the P-N junction connected to the protected nodes in the operating voltage range.

Low capacitance bidirectional transient voltage suppressor

A bidirectional transient voltage suppressor (TVS) protection circuit includes two sets of steering diodes, a clamp circuit including an MOS transistor integrated with a silicon controlled rectifier (SCR) and a trigger circuit. In response to a voltage applied to one of the protected nodes exceeding a first voltage level, the trigger circuit drives the MOS transistor to cause a current flow at the SCR to trigger an SCR action and the SCR clamps the voltage at the respective protected node at a clamping voltage. In other embodiments, a bidirectional transient voltage suppressor (TVS) protection circuit includes two sets of steering diodes with a clamp device merged with a steering diode in each set. In some embodiments, the TVS protection circuit realizes low capacitance at the protected nodes by fully or almost completely depleting the P-N junction connected to the protected nodes in the operating voltage range.

A bidirectional transient voltage suppressor (TVS) circuit for data pins of electronic devices includes two sets of steering diodes and a diode triggered clamp device in some embodiment. In other embodiments, a bidirectional transient voltage suppressor (TVS) circuit for data pins of electronic devices includes two sets of steering diodes with a clamp device merged with a steering diode in each set. The TVS circuit is constructed to realize low capacitance at the protected nodes and improved clamping voltage for robust protection against surge evens. In some embodiments, the TVS circuit realizes low capacitance at the protected nodes by fully or almost completely depleting the P-N junction connected to the protected nodes in the operating voltage range. In this manner, the TVS circuit does not present undesirable parasitic capacitance to the data pins being protected, especially when the data pins are applied in high speed applications.

The present disclosure generally relates to data storage devices, and more specifically, to a magnetic media drive employing a magnetic recording head. The head includes a trailing shield, a main pole, a MAMR stack disposed between the trailing shield and the main pole, side shields surrounding at least a portion of the main pole, and a structure disposed between the side shields and the main pole at a media facing surface (MFS). The structure is fabricated from a material that is thermally conductive and electrically insulating/dissipative. The material has a thermal conductivity of at least 50 W/(m*K) and an electrical resistivity of at least 10&#x3a9;*m. The structure helps dissipate joule heating generated from either the main pole or the MAMR stack into surrounding area without electrical shunting, leading to reduced heating or break-down induced failures.

MAMR write head with thermal dissipation conductive guide

A transient voltage suppressor (TVS) is constructed as an NPN bipolar transistor including individually optimized collector-base and emitter-base junctions both with avalanche mode breakdown. The TVS device is constructed using a base that includes a lightly doped base region bordered by a pair of more heavily doped base regions. The two more heavily doped base regions are used to form the collector-base junction and the emitter-base junction both as avalanche breakdown junctions. The lightly doped base region between the collector-base and emitter-base doping regions ensures low leakage current in the TVS device. In this manner, the TVS bipolar transistor of the present invention provides high surge protection with robust clamping while ensuring low leakage current.

High surge bi-directional transient voltage suppressor

The present disclosure generally relates to data storage devices, and more specifically, to a magnetic media drive employing a magnetic recording head. The head includes a trailing shield, a main pole, a MAMR stack disposed between the trailing shield and the main pole, side shields surrounding at least a portion of the main pole, and a structure disposed between the side shields and the main pole at a media facing surface (WS). The structure is fabricated from a material that is thermally conductive and electrically insulating/dissipative. The material has a thermal conductivity of at least 50 W/(m*K) and an electrical resistivity of at least 10&#x3a9;*m. The structure helps dissipate joule heating generated from either the main pole or the MAMR stack into surrounding area without electrical shunting, leading to reduced heating or break-down induced failures.

Ionized physical vapor deposition (IPVD) is used to form a magnetic recording disk drive write head main pole with thin side gap layers and a thicker leading gap layer. A metal or metal alloy is formed by IPVD in a trench with a bottom and outwardly sloping sidewalls. An optional Ru seed layer is deposited on the metal or metal alloy. This is followed by atomic layer deposition (ALD) of a Ru smoothing layer. If the IPVD results in metal or metal alloy side gap layers with a rough surface, the ALD process is modified, resulting in a smooth Ru smoothing layer that does not replicate the rough surface of the side gap layers.

Method for making a perpendicular magnetic recording write head with write pole having thin side gaps and thicker leading gap

The present invention generally relates to a method for forming a smooth gap of a damascene write pole. An opening having a side wall with a first angle with respect to vertical is formed in a fill layer, and a first non-magnetic layer is deposited into the opening by ion beam deposition. The ion beam is delivered to the side wall at a second angle with respect to vertical. The ratio of the first angle to the second angle ranges from about 250 to about 3.5.

Method for producing a smooth Ru side gap of a damascene writer pole

Depositing a seed layer for a high-moment shield onto a write pole may have a deleterious effect on the magnetic response of the write pole. Instead, an amorphous separation layer may be deposited between the write pole and the seed layer. In one embodiment, the seed layer is formed directly on the amorphous layer. In addition to separating the seed layer from the write pole, the amorphous separation layer permits the seed layer to dictate the crystallographic orientation of the shield which is subsequently deposited on the magnetic head. That is, the amorphous layer provides a substrate that allows the seed layer to have a crystalline structure independent of the layers that were deposited previously. The amorphous separation layer may comprise an amorphous metal&#x2014;e.g., NiNb or NiTa&#x2014;or an insulative material&#x2014;e.g., alumina or silicon dioxide.

Shield with uniform magnetic properties for a perpendicular magnetic recording head

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San Jose, CA, United States of America

Ning Shi