International Business Machines Corporation

Globalfoundries Inc.

Ning Lu

Christopher Stephen Putnam

Eric Thompson

Robert Allen Groves

Eric A Foreman

Jeffrey G Hemmett

Judith H McCullen

Cole E Zemke

Calvin John Bittner

Lawrence Alfred Clevenger

Anthony K Stamper

Zhong-Xiang He

Baozhen Li

Wilbur David Pricer

Albert Manhee Chu

Roger Allen Booth, Jr

Naftali Eliahu Lustig

Jason Eugene Stephens

Edward W Conrad

Josef S Watts

Orest Bula

Lewis William Dewey, Iii

Charles Arthur Whiting

Jim Shih-Chun Liang

Daniel C Cole

Vikrant Kumar Chauhan

Steven Alfred Grundon

Arnold E Baizley

Yoo-Mi Lee

Ralph M Alfano

Electrical structures, methods, and computer program products for radio frequency (RF) de-embedding are provided. A structure includes a first test device, a first through structure corresponding to the first test device, and a first open structure corresponding to the first test device. The structure also includes a second test device having at least one different physical dimension than the first test device but otherwise identical to the first test device, a second through structure corresponding to the second test device, and a second open structure corresponding to the second test device. A method includes determining a first electrical parameter of the first test device in a first DUT structure and a second electrical parameter of the second test device in a second DUT structure based on measured electrical parameters of the first and the second DUT structures, through structures, and open structures.

Structures and methods for RF de-embedding

According to one embodiment, a method, computer system, and computer program product for creating a plurality of process parameters in a circuit design is provided. The present embodiment of the invention may include receiving one parasitic extraction per layer of a circuit is used to obtain a resistance base factor and a capacitance base factor. The embodiment may further include performing Monte Carlo simulations to determine distributions of capacitance and resistance for each metal layer of the circuit, and creating scalars that scale each of the resistance base factor and the capacitance base factor to a minimum and maximum process limit. Additionally, the embodiment may include defining at least one delay corner using the created scalars, and receiving the results of one or more timing analyses performed using the resistance base factor and the capacitance base factor, and the defined delay corner to determine a delay variability per layer.

Method of parameter creation

An IC device, such as a wafer, chip, die, processor, application specific integrated circuit (ASIC), field programmable gate array (FPGA), or the like include a chamfered VIA that connects an upper wiring line and a first lower wiring line. The chamfered VIA includes a chamfer or fillet upon the edge that connects the VIA sidewall(s) with the VIA contact surface that is connected to the first lower wiring line. The chamfer or fillet effectively increases the amount of a dielectric material, such as a high-k dielectric material, within a trench of the VIA and that is between the chamfered VIA and a second lower wiring line that neighbors the first lower wiring line. This increased dielectric material improves TDDB between the chamfered VIA and the second lower wiring line and mitigates TDDB effects, such as electrical shorts between the chamfered VIA and the second lower wiring line.

Back end of line (BEOL) time dependent dielectric breakdown (TDDB) mitigation within a vertical interconnect access (VIA) level of an integrated circuit (IC) device

Systems and methods for applying spatial correlation in integrated circuit development involve placing devices of an integrated circuit design, and obtaining spatial correlation values. Each spatial correlation value indicates a correlation coefficient between a first device and a second device, which are instances of a same device. The correlation coefficient is based on a device separation. Spatial correlation is determined as a function of an inverse of device separation. The device separation refers to one-dimensional or two-dimensional separation. The method includes determining a parameter value for the first device based on an average value of the parameter value and on the spatial correlation as the function of the inverse of the device separation, performing analysis of the integrated circuit design using the parameter value, and providing the integrated circuit design for fabrication into an integrated circuit based on finalizing the design according to the analysis.

Characterization of spatial correlation in integrated circuit development

A system, method and computer program product for extracting integrated circuit on-chip parasitic capacitance in semiconductor structures including structures formed according to a Self-Aligned Double Patterning (SADP) semiconductor manufacturing process. A method of calculating the capacitance of a conductive signal wire in a SADP layer whose adjacent wires or groups of wires are floating (not connected to a circuit or net and not signal carrying). Further, there is provided a system running an iterative method for accurately and efficiently eliminating a group of floating metals by eliminating one floating metal wire per iteration while extracting its corresponding on-chip parasitic coupling capacitance effect. Further, system and methods calculate parasitic capacitance calculation for an 'isolated' wire(s) or a 'semi-isolated wire' resulting from employing a Self-Aligned Double Patterning (SADP) processing technique. The system and method provides a capacitance calculation and circuit simulation solution without involving use of and without computing a capacitance matrix.

Capacitance extraction method for semiconductor SADP metal wires

An approach for determining leakage current and threshold voltage for ensemble semiconductor devices, implemented in a computer infrastructure having computer executable code tangibly embodied on a computer readable storage medium having program instructions, are operable to: receive a number m of individual devices within an ensemble device; identify a sub-threshold slope; determine an uplift factor; separate random variation in logarithm of a leakage current into a correlated random component and an uncorrelated random component; determine a first standard deviation of correlated random component for the ensemble device; determine a second standard deviation of the uncorrelated random component for the ensemble device; generate a statistical model for electrical features of the ensemble device, based on the number m of individual devices, the sub-threshold slope, the uplift factor, the first and second standard deviation, and statistical random variables; and determine the electrical features of the ensemble device based on the statistical model.

Method of characterizing and modeling leakage statistics and threshold voltage for ensemble devices

Disclosed are a system and a method for integrated circuit (IC) performance modeling, wherein a design layout of an IC is analyzed to identify a first conductive shape (e.g., an internal local interconnect or contact bar shape) on a diffusion boundary shape of a semiconductor device and to also identify the first conductive shape's connectivity to any second conductive shapes (e.g., a via, via bar, or external local interconnect shapes) inside and/or outside the limits of the diffusion boundary shape. A condensed resistance model for the first conductive shape is selected from a model library based on the previously identified connectivity. The selected condensed resistance model will have a lesser number of nodes and/or resistive elements than a full resistance model for the conductive shape. The selected condensed resistance model is used to construct a condensed netlist, which is used in a combined netlist to simulate IC performance.

Integrated circuit performance modeling using a connectivity-based condensed resistance model for a conductive structure in an integrated circuit

One embodiment provides a method of building a wire resistance corner model for an interconnect metal level in a semiconductor device. The method comprises determining nominal on-wafer widths and wire thicknesses at minimum and maximum design widths of the interconnect metal level, and determining standard deviations for global variations in on-wafer width and wire thickness. The method further comprises determining maximum and minimum statistical corner values for interconnect wire resistance. A first corner solution that minimizes a maximum absolute difference between a model corner value and a statistical corner value of the maximum statistical corner values is computed. A second corner solution that minimizes a maximum absolute difference between a model corner value and a statistical corner value of the minimum statistical corner values is computed.

Building a corner model of interconnect wire resistance

A system, method and computer program product for determining correlation coefficient(s) among different field effect transistor types for a same electrical parameter type and/or among different electrical parameter types for a same field effect transistor type. The correlation coefficient(s) are determined based on the results of a limited number of simulation runs. Specifically, the number of simulation runs required by the disclosed embodiments is limited to one plus the product of the number of different field effect transistor types at issue, the number of different electrical parameter types at issue and the number of statistical process parameter types that impact the different electrical parameter types. Such correlation coefficient(s) can subsequently be used to develop a compact model of a semiconductor process technology. This compact model can then be used to perform variation-aware design of an integrated circuit chip.

Determining correlation coefficient(s) among different field effect transistor types and/or among different electrical parameter types

An approach includes deriving an uplift factor as a function of a width of the device for each leakage current component based on an amount of uncorrelated random variations in the leakage current component for one specific width and using the uplift factor as a multiplier for the leakage current component. The approach includes using the uplift factor for sub-threshold drain current as a multiplier of the sub-threshold drain current so that a lowering of nominal threshold voltage of the device occurs in a single simulation run. The approach further includes deriving a threshold voltage mismatch expression related to an amount of an uncorrelated random variation in sub-threshold drain current which is not directly inversely proportional to a square root of the width. The uplift factors and the threshold voltage mismatch expression within a model are used to predict statistical characteristics of the leakage current.

Method of characterizing and modeling leakage statistics and threshold voltage

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Essex Junction, VT, United States of America

Ning Lu