Broadcom Corporation

Ning Li

Tom W Kwan

Pieter Vorenkamp

Eric Bruce Blecker

Chao Tang

Victor Chiu-Kit Fong

Sumant Ranganathan

Jiann-Chyi Sam Shieh

Jiann-Chyi (Sam) Shieh

Jiann-chyi Shieh

Sumant Rangnathan

The present invention provides several scalable integrated circuit high density capacitors and their layout techniques. The capacitors are scaled, for example, by varying the number of metal layers and/or the area of the metal layers used to from the capacitors. The capacitors use different metallization patterns to form the metal layers, and different via patterns to couple adjacent metal layers. In embodiments, optional shields are included as the top-most and/or bottom-most layers of the capacitors, and/or as side shields, to reduce unwanted parasitic capacitance.

Scalable integrated circuit high density capacitors

The present invention provides several scalable integrated circuit high density capacitors and their layout techniques. The capacitors are scaled, for example, by varying the number of metal layers and/or the area of the metal layers used to form the capacitors. The capacitors use different metallization patterns to form the metal layers, and different via patterns to couple adjacent metal layers. In embodiments, optional shields are included as the top-most and/or bottom-most layers of the capacitors, and/or as side shields, to reduce unwanted parasitic capacitance.

An active diode includes a plurality of transistors that implement a built-in offset voltage. The built-in offset voltage size can be determined by sizing of at least one of the plurality of transistors to prevent supply current flow from one supply source into another supply source, thereby preventing current flow from a higher voltage source to a lower voltage source.

Supply voltage selector

An active diode includes a plurality of transistors and a built-in offset voltage. The built-in offset voltage size can be determined by sizing of at least one of the plurality of transistors to prevent supply current flow from one supply source into another supply source, thereby preventing current flow from a higher voltage source to a lower voltage source.

A frequency-locked clock generator includes a voltage-controlled oscillator (VCO), a frequency-to-current converter, a reference current source and a gain stage. The VCO generates an output signal. The frequency-to-current converter generates a converter current proportional to a frequency of the output signal. The reference current source generates a reference current. The gain stage generates a control signal based on a difference between the converter current and the reference current. The control signal is applied to the VCO to adjust the frequency of the output signal. Feedback forces the VCO to generate an output clock signal such that the corresponding current it produces (i.e., the converter current) is equal to the reference current. When in lock, the frequency of the output signal is determined by a time constant (or equivalent time constant) of the frequency-locked clock generator.

Frequency-locked clock generator

Embodiment of the present invention may provide a switching regulator which may be located within an IC. The switching regulator couples to an external power supply, a plurality of configurable control registers, a plurality of default registers, and a multiplexer. The multiplexer is operable to select an input control signal from either the plurality of configurable control registers or the plurality of default control registers as the output control signal to the switching regulator. This default control signal, although not optimal, allows the switching regulator to be configured in a default condition during start up or power down operations and ensures that the switching regulator may provide a stable, although not necessarily optimal, power output to the various components within the IC.

Register with default control and built-in level shifter

A charge pump circuit includes a charge pump having an output voltage. A replica circuit actively matches up and down currents in the charge pump. A charge pump bias current transistor biases the charge pump. The charge pump includes four switches driven by differential UP and DOWN signals. The charge pump includes a first tail current source connected between a supply voltage and two of the four switches that are driven by the differential UP signal, and a second tail current source connected between a supply voltage and two of the four switches that are driven by the differential DOWN signal. The charge pump includes an operational amplifier whose output is connected to an output of one of the tail current sources. A dump capacitor is connected to a negative input of the operational amplifier. The replica circuit includes four transistors, two of which match the first and second tail current sources, and the other two match the switches driven by the differential UP and DOWN signals. The replica circuit includes a second operational amplifier that matches the charge up and down current for varied output voltage. A low pass filter is at the output voltage and includes a resistor-capacitor network.

Wide output-range charge pump with active biasing current

A wide input range amplifier includes a first and second stage. The first stage has first and second inputs, first and second outputs, and first, second and third voltage sources. The first stage accepts input signals having a first common mode voltage range and outputs a first output signal having a second common mode voltage range and being amplified a first amount. The second stage has first and second inputs connected to the first and second outputs of the first stage, respectively. The second stage accepts input signals having a common mode voltage in the second range and outputs a second output signal having a third common mode voltage range and being amplified a second amount.

Wide common mode differential input amplifier and method

A differential driver includes a switching module and first and second voltage controlled voltage sources. The switching module has a plurality of switches each controlled by an input signal, a first voltage input and a second voltage input, and a signal output. The first voltage controlled voltage source is connected to the first voltage input. The first voltage controlled voltage source has a low impedance. The second voltage controlled voltage source is connected to the second voltage input. The second voltage controlled voltage source also has a low impedance. The switching circuit outputs an output signal having an output voltage and current controlled by the first and second voltage controlled voltage sources. The output signal is based upon the input signal.

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Fremont, CA, United States of America

Ning Li