International Business Machines Corporation

Applied Materials, Inc.

King Abdulaziz City for Science and Technology

University of Michigan

Washington University

Globalfoundries Inc.

Elpis Technologies Inc.

Ning Li

Devendra K Sadana

Stephen W Bedell

Effendi Leobandung

Talia S Gershon

Yun Seog Lee

Mihaela A Balseanu

Cheng-Wei Cheng

Ghavam G Shahidi

Teodor Krassimirov Todorov

Joel Pereira De Souza

Kuen-Ting Shiu

Li-Qun Xia

Qing Cao

Jeehwan Kim

Jean-Olivier Plouchart

Jianshi Tang

Steven J Holmes

Keith E Fogel

Mark Joseph Saly

Katherine Lynn Saenger

Frank Robert Libsch

Bahman Hekmatshoartabari

Joshua T Smith

Russell Alan Budd

Huan Hu

Tak H Ning

Bing Dang

Yann A Astier

Shu-Jen Han

Paul Alfred Lauro

Patryk Gumann

Bhaskar Jyoti Bhuyan

Sean Hart

Victor Nguyen

Davood Shahrjerdi

Robert L Wisnieff

Brent A Wacaser

Jean-Oliver Plouchart

David P Thompson

Xiao Hu Liu

Eugene Jon Shekita

Chao Wang

Arvind Kumar

Babar Ali Khan

Tze-Chiang Chen

Katsuyuki Sakuma

Kevin W Brew

Kevin Griffin

Hui-I Hsiao

Ko-Tao Lee

Wanki Kim

Kunal Mukherjee

Stephen R Forrest

Hariklia Deligianni

John C Forster

George Stojan Tulevski

Jin Cai

Ronald Jason Barber

Roger C Raphael

Bruce Gilbert Lindsay

James Bowler Hannon

Tsutomu Tanaka

Leathen Shi

Kevin Scott Beyer

Thomas Knisley

Ronny Lempel

Sridhar Rajagopalan

Can Bayram

Atashi Basu

Volker J Sorger

Satoshi Oida

Guy M Cohen

Abhijit Basu Mallick

Theodore Gerard Van Kessel

Fei Liu

Anchuan Wang

Roy Rongqing Yu

Tymon Barwicz

Oki Gunawan

Seyoung Kim

Qiqing Christine Ouyang

John Albrecht Ott

Tayfun Gokmen

Chitra K Subramanian

Harold John Hovel

Suketu Arun Parikh

Jared Barney Hertzberg

Seshadri Subbanna

David C Mckay

Paul Sherwood Taylor

Sanjay S Natarajan

Jianxin Lei

Tomohiko Kitajima

Hung-Yang Chang

Dongqing Yang

Fabio Carta

Rajesh Prasad

Gill Yong Lee

Sung-Kwan Kang

Provided are self-aligned double patterning methods including feature trimming. The SADP process is performed in a single batch processing chamber in which the substrate is laterally moved between sections of the processing chamber separated by gas curtains so that each section independently has a process condition.

Self-aligned double patterning with spatial atomic layer deposition

A cross-point memory semiconductor structure and a method of creating the same are provided. There is a first electrode layer on top of the substrate. A conductive oxide diffusion barrier layer is on top of the first electrode. A polycrystalline silicon diode is on top of the conductive oxide diffusion barrier. A phase change material (PCM) layer is on top of the polycrystalline silicon diode. A second electrode is on top of the PCM layer.

Conductive oxide diffusion barrier for laser crystallization

Processing methods for forming a silicon nitride film comprising exposing a metal surface to a silicon precursor, a nitrogen-containing reactant and a hydrogen-containing plasma at a temperature less than or equal to about 250° C. to form a silicon nitride film with a low etch rate without damaging the metal surface.

Methods and apparatus for low temperature silicon nitride films

Methods and apparatus for processing a substrate are provided herein. For example, a method of processing a substrate comprises a) removing oxide from a metal layer disposed in a dielectric layer on the substrate disposed in a processing chamber, b) selectively depositing a self-assembled monolayer (SAM) on the metal layer using atomic layer deposition, c) depositing a precursor while supplying water to form one of an aluminum oxide (AlO) layer on the dielectric layer or a low-k dielectric layer on the dielectric layer, d) supplying at least one of hydrogen (H) or ammonia (NH) to remove the self-assembled monolayer (SAM), and e) depositing one of a silicon oxycarbonitride (SiOCN) layer or a silicon nitride (SiN) layer atop the metal layer and the one of the aluminum oxide (AlO) layer on the dielectric layer or the low-k dielectric layer on the dielectric layer.

Methods and apparatus for selective etch stop capping and selective via open for fully landed via on underlying metal

A bottom electrode, a phase change material layer, the phase change material layer includes a similar lattice constant as a lattice constant of the bottom electrode, and a top electrode vertically aligned. A phase change material layer, a top electrode adjacent to a first vertical side surface of the phase change material layer, and a bottom electrode adjacent to a second vertical side surface of the phase change material layer. Forming a phase change material layer, forming a top electrode adjacent to a first vertical side surface and overlapping a first portion of an upper horizontal surface of the phase change material layer, forming a bottom electrode, adjacent to a second vertical side surface and overlapping a second portion of the upper horizontal surface of the phase change material layer, and forming a dielectric material horizontally isolating the bottom electrode and the top electrode.

Crossbar memory array in back end of line

A crystallization seed layer in a substrate, a phase change material layer, the phase change material layer includes a similar lattice constant as a lattice constant of the crystallization seed layer, a top electrode adjacent to a first vertical side surface and a bottom electrode adjacent to a second vertical side surface of the phase change material layer. A plurality of memory structures configured in a crossbar array, each including a crystallization seed layer, a phase change material layer above, a top electrode adjacent to a first vertical side surface and a bottom electrode adjacent to a second vertical side surface of the phase change material layer. A method including forming a crystallization seed layer, forming a phase change material layer, forming a top electrode and a bottom electrode on the substrate, each adjacent to a vertical side surface of the phase change material layer.

Crossbar memory array in back end of line with crystallization front

A method for forming a pumped laser structure includes forming a III-V buffer layer on a substrate including one of Si or Ge; forming a light emitting diode (LED) on the buffer layer configured to produce a threshold pump power; forming a photonic crystal layer on the LED and depositing a monolayer semiconductor nanocavity laser on the photonic crystal layer for receiving light through the photonic crystal layer from the LED with an optical pump power greater than the threshold pump power, wherein the LED and the laser are formed monolithically and the LED functions as an optical pump for the laser.

Nanocavity monolayer laser monolithically integrated with LED pump

A computing device is provided. The computing device includes a sapphire substrate having a first surface and a second surface opposed to the first surface, a light receiving device having a first surface and a second surface opposed to the first surface, the second surface of the light receiving device coupled to the first surface of the sapphire substrate, a memory coupled to the first surface of the light receiving device, and an antenna coupled to the first surface of the sapphire substrate.

Silicon on sapphire substrate for edge computer

A deposition system includes a deposition source and a scanning stage disposed within a deposition path of the deposition source. The scanning stage includes a support platform configured to support a wafer thereon, and a mechanical actuator coupled to the support platform. The mechanical actuator is configured to translate the support platform with respect to the deposition source. The deposition system includes a proximity mask disposed within the deposition path of the deposition source between the deposition source and the scanning stage, the proximity mask defining a slit. The deposition system includes a controller in communication with the scanning stage, the controller configured to control the mechanical actuator to translate the wafer with respect to the slit such that an angle of deposition remains substantially constant. In operation, the proximity mask prevents deposition source material having a trajectory that is out of alignment with the slit from contacting the wafer.

Cluster tool for production-worthy fabrication of Dolan bridge quantum Josephson junction devices

A phase change memory (PCM) structure configured for performing a gradual reset operation includes first and second electrodes and a phase change material layer disposed between the first and second electrodes. The PCM structure further includes a thermal insulation layer disposed on at least sidewalls of the first and second electrodes and phase change material layer. The thermal insulation layer is configured to provide non-uniform heating of the phase change material layer. Optionally, the thermal insulation layer may be formed as an air gap. The PCM structure may be configured having the first and second electrodes aligned in a vertical or a lateral arrangement.

Phase change memory having gradual reset

Methods of manufacturing memory devices are provided. The methods improve the quality of a selectively deposited silicon-containing dielectric layer. The method comprises selectively depositing a silicon-containing dielectric layer in a recessed region of a film stack. The selectively deposited silicon-containing dielectric layer is then exposed to a high-density plasma and annealed at a temperature greater than 800 ° C. to provide a silicon-containing dielectric film having a wet etch rate of less than 4 Å/min.

Sequential plasma and thermal treatment

Compound semiconductor and silicon-based structures are epitaxially formed on semiconductor substrates and transferred to a carrier substrate. The transferred structures can be used to form discrete photovoltaic and light-emitting devices on the carrier substrate. Silicon-containing layers grown on doped donor semiconductor substrates and compound semiconductor layers grown on off-cut semiconductor substrates form elements of the devices. The carrier substrates may be electrically insulating substrates or include electrically insulating layers to which photovoltaic and/or light-emitting structures are bonded.

Device integration using carrier wafer

A gated Josephson junction includes a substrate and a vertical Josephson junction formed on the substrate and extending substantially normal the substrate. The vertical Josephson junction includes a first superconducting layer, a semiconducting layer, and a second superconducting layer. The first superconducting layer, the semiconducting layer, and the second superconducting layer form a stack that is substantially perpendicular to the substrate. The gated Josephson junction includes a gate dielectric layer in contact with the first superconducting layer, the semiconducting layer, and the second superconducting layer at opposing side surfaces of the vertical Josephson junction, and a gate electrically conducting layer in contact with the gate dielectric layer. The gate electrically conducting layer is separated from the vertical Josephson junction by the gate dielectric layer. In operation, a voltage applied to the gate electrically conducting layer modulates a current through the semiconducting layer of the vertical Josephson junction.

Superconductor-semiconductor Josephson junction

A method of producing a quantum circuit includes forming a mask on a substrate to cover a first portion of the substrate, implanting a second portion of the substrate with ions, and removing the mask, thereby providing a nanowire. The method further includes forming a first lead and a second lead, the first lead and the second lead each partially overlapping the nanowire. In operation, a portion of the nanowire between the first and second leads forms a quantum dot, thereby providing a quantum dot Josephson junction. The method further includes forming a third lead and a fourth lead, one of the third and fourth leads partially overlapping the nanowire, wherein the third lead is separated from the fourth lead by a dielectric layer, thereby providing a Dolan bridge Josephson junction. The nanowire is configured to connect the quantum dot Josephson junction and the Dolan bridge Josephson junction in series.

Combined Dolan bridge and quantum dot Josephson junction in series

Methods and apparatus for forming a conformal SiCON film on a surface are described. A SiCN film is formed on a substrate surface and exposed to a low temperature steam annealing process to form a film resistant to damage by rapid thermal processing or ashing. The film is treated by rapid thermal processing and then subjected to a high temperature anneal to form a film with a low dielectric constant.

Methods and apparatus for deposition of low-k films

Growing community of inventors

White Plains, NY, United States of America

Ning Li