International Business Machines Corporation

Other

Ning Hsieh

Chung H Lam

Charles W Koburger, Iii

Howard L Kalter

Larry Alan Nesbit

Clinton C Kuo

Gary Douglas Grise

Mousa H Ishaq

Henry J Geipel, Jr

Stanley Roberts

Eugene A Irene

A single transistor EEPROM cell utilizes a tunneling oxide erase mechanism in which the tunneling oxide overlies a portion of the channel region. In addition, an array of single transistor EEPROM cells having a layout which provides convenient byte-at-a-time erase and program operation is disclosed. Two bytes of the array along adjacent rows share a common source, which also forms the source of a pair of erase select transistors, one for each byte. The word lines/control gates of the two bytes form the gates of the two erase select transistors.

Single transistor cell for electrically-erasable programmable read-only

An improved method of fabricating a stable high dielectric constant and low leakage dielectric material includes oxidizing at a temperature of about 400.degree. C. or higher a layer of a transition metal-silicon alloy having 40% to 90% transition metal by atomic weight to produce a silicate or homogeneous mixture. The mixture includes an oxide of the transition metal and silicon dioxide. The alloy may be deposited on, e.g., a semiconductor or an electrically conductive layer that is oxidation resistant, and the thickness of the mixture or oxidized alloy should be within the range of 5 to 50 nanometers. By depositing an electrically conductive layer on the homogeneous mixture, a capacitor having a high dielectric, low leakage dielectric medium is provided.

Method of making high dielectric constant insulators and capacitors

A method of providing self-passivating interconnection electrodes for semiconductor devices which provides low resistivity composite polysiliconsilicide electrodes. In the method the formation of oxidation induced voids in polysilicon underlying the silicide is eliminated by deposition of polysilicon and stoichiometric proportions of silicon and a silicide-forming metal. These steps are followed by deposition of a silicon layer having a thickness determined to provide between 30 and 100 percent of the silicon required to form a silicon dioxide passivation layer. Subsequent thermal oxidation of the layered electrode structure provides a self-passivated structure useful for fabrication of silicon gate MOSFET devices as well as other integrated circuit structures.

Fabrication method for high conductivity, void-free polysilicon-silicide

This invention provides an improved electrically alterable read only memory system which includes a semiconductor substrate having a diffusion region therein defining one end of a channel region, a control plate, a floating plate separated from the channel region by a thin dielectric layer and disposed between the control plate and the channel region and means for transferring charge to and from the floating plate. A control gate is coupled to the channel region and is located between the diffusion region and the floating plate. The control gate may be connected to a word line and the diffusion region may be connected to a hit/sense line. The channel region is controlled by the word line and the presence or absence of charge on the floating plate. Thus, information may be read from a cell of the memory by detecting the presence or absence of charge stored in the inversion capacitor under the floating plate. The charge transfer means includes an enhanced conduction insulator and means for applying appropriate voltages to the control plate and to the control gate to transfer charge to and from the floating plate through the enhanced conduction insulator.

Dense electrically alterable read only memory

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San Jose, CA, United States of America

Ning Hsieh