Hewlett-Packard Development Company, L.p.

Tetramem Inc.

Hewlett Packard Enterprise Development LP

Other

Tetramen Inc.

Ning Ge

Jianhua Yang

Minxian Max Zhang

Helen Ann Holder

Steven J Simske

Miao Hu

Zhiyong Li

John Paul Strachan

Anita Rogacs

Leong Yap Chia

Viktor Shkolnikov

Steven J Barcelo

Adam L Ghozeil

Wai Mun Wong

Lihua Zhao

Trudy L Benjamin

Wenbo Yin

Robert Ionescu

Jose Jehrome Rando

Boon Bing Ng

Jarrid Wittkopf

Joseph M Torgerson

Paul J Benning

Paul Howard Mazurkiewicz

Chaw Sing Ho

Patrick Leonard

Bee Ling Peh

Richard Stanley Williams

Thida Ma Win

Mun Hooi Yaow

Michael W Cumbie

Chandrakant D Patel

Jun Zeng

Brent Buchanan

George H Corrigan

Neel Banerjee

David George

Teck-Khim Neo

Pin Chin Lee

Mingche Wu

Ser Chia Koh

Chien-Hua Chen

Alexander N Govyadinov

Charles Santori

Andrew E Fitzhugh

Paul I Mikulan

Reynaldo V Villavelez

Kyung Min Kim

Milo Overbay

Richard James Auletta

Katy Samuels

Ya-Ling Chang

Eric T Martin

Frederick A Perner

James Michael Gardner

Daryl E Anderson

Warren Bruce Jackson

Gary A Gibson

Ian N Robinson

Naveen Muralimanohar

Janice H Nickel

Tom J Searby

Huei Pei Kuo

Craig Peter Sayers

James Elmer Abbott, Jr

Erik D Ness

Vincent Hung Nguyen

Robert G Walmsley

Hiroshi Horii

David B Novak

Peter Andrew Seiler

Rafael A Ballagas

Raphael Gay

Chanh V Hua

Kevin Dooley

Teck Khim Neo

John Oliver

Lei Liu

Alexander Thayer

Glen Eric Montgomery

Kenneth Hickey

James E Abbott

Rongliang Zhou

Hengfang Zhu

Tyler Sims

Shane O'Brien

Jianhui Gu

Junrui Yang

Max Zhang

Jianwen Luo

Hang-Ru Goy

Ken Kiat Ng

Ya Ling Chang

Ralph A Morales

Terrance J OShea

R Stanley Williams

Hafid Hamadene

Mingyi Rao

James Elmer Abbott Jr

The present disclosure provides read-out circuits for crossbar circuits. A crossbar circuit may include a plurality of bit lines intersecting with a plurality of word lines and a plurality of cross-point devices. Each of the plurality of cross-point devices is connected to at least one of the plurality of word lines and at least one of the plurality of bit lines. The crossbar circuit may further include an output sensor that generates a digital output representative of a sum of currents flowing through one or more bit lines of the crossbar circuit. The output sensor includes a first transistor serially connected to a second transistor and an analog-to-digital converter configured to output the digital output. The read-out circuit is an open loop circuit. The read-out circuit may be selectively connected to one of the plurality of bit lines to perform a read operation.

Read-out circuits for RRAM-based crossbar circuits

In accordance with some embodiments of the present disclosure a tunneling-based selector is provided. The selector includes a multilayer barrier structure fabricated between a first electrode and a second electrode. The multilayer barrier structure includes a first layer of a first van der Waals (vdW) material; a second layer of a second vdW material; and a third layer of a third vdW material. The first layer of the first vdW material is fabricated between the second layer of the second vdW material and the third layer of the third vdW material. The electron affinity of the first layer of the first vdW material is lower than the second electron affinity of the second layer of the second vdW material and the electron affinity of the third layer of the vdW material.

Tunneling-based selectors incorporating van der Waals (vdW) materials

Technologies relating to RRAM crossbar array circuits with specialized interface layers for the low current operations are disclosed. An example apparatus includes: a substrate; a bottom electrode formed on the substrate; a first layer formed on the bottom electrode; an RRAM oxide layer formed on the first layer and the bottom electrode; and a top electrode formed on the RRAM oxide layer. The first layer may be a continuous layer or a discontinuous layer. The apparatus may further comprise a second layer formed between the RRAM oxide layer and the top electrode. The second layer may be a continuous layer or a discontinuous layer.

Methods for fabricating RRAM crossbar array circuits with specialized interface layers for low current operation

A crossbar circuit including a crossbar array and a periphery circuit is provided. A resistive random-access memory (RRAM) device of the crossbar array includes a bottom electrode fabricated on a first interconnect layer; a top electrode; and a filament-forming layer fabricated between the bottom electrode and the top electrode. A portion of the filament-forming layer and a portion of the top electrode are fabricated in a via in a first etch stop layer. The crossbar circuit further includes a second etch stop layer fabricated on the top electrode and a dielectric layer fabricated on the second etch stop layer. The top electrode is connected to a first metal via of a second interconnect layer fabricated in the second etch stop layer and the dielectric layer. The periphery circuit includes a metal via of the second interconnect layer that is fabricated in the dielectric layer and the first etch stop layer.

CMOS-compatible resistive random-access memory devices with a via device structure

A crossbar circuit is provided. The crossbar circuit includes one or more bit lines, one or more word lines, one or more cell devices connected between the bit lines and the word lines, one or more analog-to-digital converters (ADCs) connected to the one or more bit lines, one or more digital-to-analog converters (DACs) connected to the one or more word lines, one or more access controls connected to the one or more cell devices and configured to select a cell device in the one or more cell devices and to program the selected cell device, and a slew rate controller connected to the one or more bit lines. The first slew rate controller is configured to receive an input signal or a bias and output a slew-rate controlled signal.

Reducing disturbance in crossbar array circuits

In accordance with some embodiments of the present disclosure, a memory device is provided. The memory may include a ferroelectric layer including a ferroelectric material interstitially doped with at least one interstitial dopant. The ferroelectric material may include a metal oxide. The interstitial dopant may include an element having an atomic radius that is not greater than an atomic radius of a metal element of the metal oxide. In some embodiments, the metal oxide comprises at least one of hafnium or zirconium. The memory device may be non-volatile. The memory device may be a ferroelectric capacitor (FeCAP), a ferroelectric field-effect transistor (FeFET), a ferroelectric tunneling junction (FTJ), and/or another form of ferroelectric random-access memory (Fe-RAM).

Ferroelectric non-volatile memory devices

Code comparators with nonpolar dynamical switches are provided. An example apparatus comprises: a plurality of row wires; a plurality of column wires; one or more cross-point devices, and a nonpolar volatile two-terminal device formed within a plurality of cross-point devices. Each cross-point device in the plurality of cross-point devices is located at a cross-point between a row in the plurality of row wires and a column in the plurality of column wires; the nonpolar volatile two-terminal device is configured to automatically revert from an ON state to an OFF state, in response to a removal of a bias or signal applied on the nonpolar volatile two-terminal device. The nonpolar volatile two-terminal device is configured to automatically revert from an ON state to an OFF state, in response to a removal of a bias or signal applied on the nonpolar volatile two-terminal device.

Code comparators with nonpolar dynamical switches

Technologies for reducing series resistance are disclosed. An example method may include: forming a first layer on a temporary substrate; forming a second layer on the first layer; etching the first layer and the second layer to form a trench; electroplating a top electrode via the trench, wherein the top electrode partially formed on a top surface of the second layer; removing the first layer and the second layer; forming a curable layer on the temporary substrate and the top electrode; removing the temporary substrate from the curable layer and the top electrode; forming a cross-point device on the curable layer and the top electrode; forming a bottom electrode on the cross-point device; and forming a flexible substrate on the bottom electrode.

Large-scale crossbar arrays with reduced series resistance

The present disclosure provides mechanisms for reducing and suppressing random telegraph noise (RTN) for a crossbar circuit. A processing device may perform a programming process to program the conductance of a resistive random-access memory (RRAM) device in the crossbar circuit to a target conductance value. The processing device may then determine whether a random telegraph noise (RTN) value associated with the RRAM device is within a predetermined range of acceptable RTN values. If the RTN value associated with the RRAM device is not within a predetermined range of acceptable RTN values, one or more noise-reduction voltages may be applied to the RRAM device until the RTN value associated with the RRAM device is within the predetermined range of acceptable RTN values.

Suppressing random telegraph noise in crossbar circuits

The present disclosure relates to resistive random-access memory (RRAM) devices. A method for fabricating resistive random-access memory (RRAM) device may include fabricating, on a first electrode of the RRAM device, a first interface layer comprising a first discontinuous film of a first material; fabricating, on the first interface layer, a switching oxide layer comprising at least one transition metal oxide; fabricating a second interface layer on the switching oxide layer; and fabricating a defect engineering layer on the second interface layer. The first material is more chemically stable than the at least one transition metal oxide. The defect engineering layer includes a layer of Ti in some embodiments.

Resistive random-access memory devices with engineered electronic defects and methods for making the same

The present disclosure relates to resistive random-access memory (RRAM) devices. An RRAM device may include a first electrode, a first interface layer fabricated on the first electrode; a switching oxide layer fabricated on the first interface layer; and a second electrode fabricated on the switching oxide layer. The switching oxide layer includes a transition metal oxide. The first interface layer includes a discontinuous film of a first material that is more chemically stable than the transition metal oxide. The RRAM device may further include a second interface layer positioned between the switching oxide layer and the second electrode. The second interface layer includes a discontinuous film of a second material that is more chemically stable than the transition metal oxide. The second electrode may include multiple electrode components that may include an alloy, a first layer of a first metallic material, and/or a second layer of a second metallic material.

Resistive random-access memory devices with multi-component electrodes and discontinuous interface layers

The present disclosure provides for transimpedance amplifiers for crossbar circuits. A crossbar circuit may include a plurality of bit lines intersecting with a plurality of word lines and a plurality of cross-point devices. Each of the plurality of the cross-point devices is connected to at least one of the word lines and at least one of the bit lines. The crossbar circuit may further include a transimpedance amplifier to generate an output voltage representative of a sum of currents flowing through a first bit line of the plurality of bit line. The transimpedance amplifier may include an operational amplifier, a current mirror circuit connected to an output of the operational amplifier, and one or more resistors connected to the current mirror circuit and a supply voltage.

Transimpedance amplifiers for crossbar circuits

Technologies relating to crossbar array circuits with parallel ground lines are disclosed. An example crossbar array circuit may include a plurality of transistors. The crossbar array circuit may include an RRAM device connected in series with a first transistor and a second transistor; a first bit line connected to the RRAM device; and a grounding line connected to a body terminal of the first transistor. The grounding line is parallel to the first bit line. In some embodiments, the first transistor is an NMOS transistor. The second transistor is a PMOS transistor.

Crossbar array circuit with parallel grounding lines

The present disclosure relates to resistive random-access memory (RRAM) devices. In some embodiments, a RRAM device may include a first electrode; a second electrode comprising an alloy containing tantalum; and a switching oxide layer positioned between the first electrode and the second electrode, wherein the switching oxide layer includes at least one transition metal oxide. The alloy containing tantalum may further contain at least one of hafnium, molybdenum, tungsten, niobium, or zirconium. In some embodiments, the alloy containing tantalum may include one or more of a binary alloy containing tantalum, a ternary alloy containing tantalum, a quaternary alloy containing tantalum, a quinary alloy containing tantalum, a senary alloy containing tantalum, and a high order alloy containing tantalum.

Resistive random-access memory devices with multi-component electrodes

The present disclosure provides for a semiconductor device with integrated sensing and processing functionalities. The semiconductor device includes a sensing module configured to generate a plurality of analog sensing signals; and a machine learning (ML) processor. The sensing module and the ML processor are fabricated on a single wafer. The ML processor includes crossbar arrays that processes the analog sensing signals to generate analog preprocessed sensing data; an analog-to-digital converter (ADC) to convert the analog preprocessed sensing data into digital preprocessed sensing data; and a machine learning processing unit to process the digital preprocessed sensing data utilizing one or more machine learning model.

Integrated sensing and machine learning processing devices

Growing community of inventors

Palo Alto, CA, United States of America

Ning Ge