Spansion LLC.

Advanced Micro Devices Corporation

Altera Corporation

Cypress Semiconductor Corporation

Intel Corporation

Globalfoundries Inc.

Altera Corporaton

Ning Cheng

Angela Tai Hui

Minh Van Ngo

Hiroyuki Kinoshita

Huaqiang Wu

Hiro Kinoshita

Minghao Shen

Andy Louie Lee

Kuo-Tung Chang

Jihwan Choi

Kyunghoon Min

Mark T Ramsbey

Jeffrey Allan Shields

Jean Y Yang

Wenmei Li

Jaeyong Park

Hirokazu Tokuno

Jeff P Erhardt

Cyrus E Tabery

Chih-Yuh Yang

Tazrien Kamal

Lei Xue

Robert A Huertas

Shankar Sinha

Ashot Melik-Martirosian

Fangyun Richter

Fred Cheung

Tyagamohan Gottipati

Clarence B Ferguson

Mark S Chang

Kouros Ghandehari

Amol Ramesh Joshi

Chungho Lee

Cinti Xiaohua Chen

Calvin T Gabriel

Arvind Halliyal

Hidehiko Shiraiwa

Timothy J Thurgate

Wei Zheng

Jean Yee-Mei Yang

Harpreet Kaur Sachar

Emmanuil Lingunis

Pei-Yuan Gao

Jeffrey Xiaoqi Tung

Che Ta Hsu

Phillip Lawrence Jones

Michael Brennan

James K Pan

Christy Mein Chu Woo

Fei Wang

Paul Raymond Besser

Mahesh A Iyer

Shenqing Fang

Lu You

Chi K Chang

Christy Mei-Chu Woo

Peter Smeys

Dawn M Hopper

Simon S Chan

Yi He

Unsoon Kim

Ankur Agarwal

Alexander H Nickel

Minh Quoc Tran

Rinji Sugino

Krishnashree Achuthan

Hung-Eil Kim

Zhiyuan Wu

Connie Pin-Chin Wang

Minh-Van Ngo

Christopher J Pass

Jinsong Yin

Anna Maria Minvielle

Patrick K Cheung

Wai Lo

Joerg Reiss

John Caffall

Sung Jin Kim

Christie R K Marrian

Kevin Song

Huade Walter Yao

Xiangyong Wang

Russell Rosaire Austin Callahan

Jeremy Chi-Hung Chou

Brian Mooney

Jean Yei-Mei Yang

Jeyong Park

Arturo Ruiz

Sugino Rinji

Norimitsu Takagi

Brian Osborn

An integrated circuit with programmable logic circuitry is provided. The integrated circuit may include quiet regions, toggling regions, or unused regions. An integrated circuit may also include heavily-used metal routing paths, lightly-used metal routing paths, and unused metal routing paths. Circuit design tools may be used to generate multiple configuration images that replace the quiet regions with toggling or unused regions, that swap the heavily-used metal routing paths with lightly-used or unused metal routing paths, or that use random fitter seeds of improve the usage coverage to statistically reduce the always quiet regions on the integrated circuit. The multiple configuration images implement the same design and can be used to reconfigure the integrated circuit upon startup to reduce aging effects and improve circuit performance.

Methods and apparatus for reducing reliability degradation on an integrated circuit

Fabrication methods for monolithic dies that integrate multiple integrated circuits, such as System-on-Chips are described. A substrate having an interconnect may be coupled via electrical terminations to the integrated circuits. Fabrication methods provide multiple electrical termination regions on a surface, with each region having geometrical properties that are appropriate for the coupled integrated circuit. Electrical terminations with different directions may be produced employing a single reactive ion etching process under conditions that enhance micro loading effects during fabrication.

Manufacture of interconnects for integration of multiple integrated circuits

A transistor device is provided. The transistor device includes a group of fins formed in a substrate, where the group of fins comprises at least one enabled fin and at least one disabled fin. Each of the fins has first and second fin portions. The first fin portion encompasses a drain region and the second fin portion of the fins encompasses a source region. These two regions are separated by a channel region. A gate structure is formed over the fins and channel region and in between the first fin portion and the second fin portion of the fins. The transistor device further includes a conductive structure. The conductive structure shorts the first fin portion of the at least one disabled fin to the second fin portion of the at least one disabled fin.

Methods and apparatuses for optimizing power and functionality in transistors

Integrated circuits may include partial reconfiguration (PR) circuitry for reconfiguring only a portion of a memory array. In some applications, partial reconfiguration may be performed during user mode. During partial reconfiguration, write assist techniques such as varying the power supply voltage may be applied to help increase write margin, but doing so can potentially affect the performance of in-operation pass gates that are being controlled by the memory array during user mode. In one suitable arrangement, ground power supply voltage write assist techniques may be implemented on memory cells that include p-channel access transistors and that are used to control n-channel pass transistors. In another suitable arrangement, positive power supply voltage write assist techniques may be implemented on memory cells that include n-channel access transistors and that are used to control p-channel pass transistors.

Programmable integrated circuits with in-operation reconfiguration capability

A method of fabricating an integrated circuit includes forming a plurality of polysilicon gate electrode structures over a plurality of fin-shaped channel structures. A portion of the plurality of polysilicon gate electrode structures may then be removed to expose a surface region of a fin-shaped channel structure in the plurality of fin-shaped channel structures. The remaining portion of the polysilicon gate electrode structures may form a plurality of polysilicon transistors. A layer of high-k dielectric material is deposited on the exposed surface region of the fin-shaped channel structure. A metal layer may be deposited over the high-k dielectric material to form at least one high-k metal gate transistor over the fin-shaped channel structure.

Methods for fabricating integrated circuits with triple gate oxide devices

Memory devices having an increased effective channel length and/or improved TPD characteristics, and methods of making the memory devices are provided. The memory devices contain two or more memory cells on a semiconductor substrate and bit line dielectrics between the memory cells. The memory cell contains a charge trapping dielectric stack, a poly gate, a pair of pocket implant regions, and a pair of bit lines. The bit line can be formed by an implant process at a higher energy level and/or a higher concentration of dopants without suffering device short channel roll off issues because spacers at bit line sidewalls constrain the implant in narrower implant regions.

HTO offset for long leffective, better device performance

A FinFET comprises a substrate, an array of substantially parallel fins formed on the substrate and extending in a first direction, and an array of gates on the fins. First gates extend across the same fins of a first plurality of the fins in a second direction transverse to the first. Second gates extend across the same fins of a second plurality of fins in the second direction; the second gates having a length that is larger than that of the first gates. Third gates extend across the same fins of a third plurality of fins in the second direction; the third plurality of fins being located between the first and second pluralities. The third gates provide a transition between the first gates and the second gates in which a first portion of the third gates are dummies and a second portion are active devices such as pass gates.

Power and die size optimization in FinFETs

Memory devices having improved TPD characteristics and methods of making the memory devices are provided. The memory devices contain two or more memory cells on a semiconductor substrate and bit line openings containing a bit line dielectric between the memory cells. The memory cell contains a charge storage layer and a first poly gate. The bit line opening extends into the semiconductor substrate. By containing the bit line dielectric in the bit line openings that extend into the semiconductor substrate, the memory device can improve the electrical isolation between memory cells, thereby preventing and/or mitigating TPD.

Oro and orpro with bit line trench to suppress transport program disturb

Methods are provided for fabricating memory devices. A method comprises fabricating charge-trapping stacks overlying a silicon substrate and forming bit line regions in the substrate between the charge trapping stacks. Insulating elements are formed overlying the bit line regions between the stacks. The charge-trapping stacks are etched to form two complementary charge storage nodes and to expose portions of the silicon substrate. Silicon is grown on the exposed silicon substrate by selective epitaxial growth and is oxidized. A control gate layer is formed overlying the complementary charge storage nodes and the oxidized epitaxially-grown silicon.

Method of forming spaced-apart charge trapping stacks

In an illustrative embodiment, holes are formed in an insulating layer where the gates of NMOS and PMOS transistors are to be formed; and a hard mask spacer layer is formed on the exposed surfaces. Next, spacers are formed on the sidewalls of the holes by anisotropically etching the spacer layer to remove the portion of the spacer layer exposed at the bottom of each hole while leaving some of the spacer layer formed on the sidewalls of the holes. A high-k dielectric layer is then formed between the spacers; and a metal layer is formed on the high-k dielectric layer. Bulk metal layer is then formed on the metal layer. Chemical mechanical polishing is performed to remove the bulk gate metal down to the insulating layer, thereby isolating individual NMOS and PMOS gate structures.

High-k dielectric device and process

A plurality of elongated, substantially parallel mandrels are formed on a first work surface, the mandrels being spaced apart a distance in the range between the resolution limit and twice the resolution limit. Spacers are formed on the work surface extending from sidewalls of the mandrels. First portions of the work surface are exposed through gaps in the spacers near the midpoint between a majority of adjacent mandrels; but at least one pair of adjacent mandrels is close enough together that the spacers extend continuously between the adjacent mandrels. The mandrels are then removed, thereby exposing second portions of the work surface. The exposed first and second portions are etched down to a second work surface; and the exposed portions of the second work surface are etched to form trenches in that surface. A wire routing is formed by filling the trenches with a metal such as copper.

Metal routing in advanced process technologies

An insulating layer is formed on a semiconductor substrate; and holes are patterned in the insulating layer where transistor gates are to be formed. A hard mask spacer layer is formed on the upper surface of the insulating layer and the holes. Next, the spacer layer is anisotropically etched to remove the portion of the spacer layer exposed at the bottom of each hole as well as the portion of the spacer layer on the upper surface of the insulating layer. However, the etching process does not remove all of the portion of the spacer layer formed on the substantially vertical sidewalls of the holes. A high-k dielectric layer is then formed on the remaining vertical portion of the spacer layer and on the exposed upper surfaces of the substrate and the insulating layer. A metal layer is then formed on the high-k dielectric layer; and individual gate structures are completed.

Flash memory devices and methods for fabricating the same are provided. In accordance with an exemplary embodiment of the invention, a method for fabricating a memory device comprises the steps of fabricating a first gate stack and a second gate stack overlying a substrate. A trench is etched into the substrate between the first gate stack and the second gate stack and a first impurity doped region is formed within the substrate underlying the trench. The trench is filled at least partially with a conductive material.

Flash memory devices and methods for fabricating same

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San Jose, CA, United States of America

Ning Cheng