Silicon Storage Technology, Inc.

Ning Bai

Xiaozhou Qian

Kai Man Yue

Nhan Do

Jinho Kim

Yao Zhou

Hieu Van Tran

Tao Wang

Vipin Tiwari

Xian Liu

Yuri Tkachev

Parviz Ghazavi

Bin Sheng

Qing Rao

Lu Guo

The present invention relates to an improved sense amplifier for reading values in flash memory cells in an array. In one embodiment, a sense amplifier comprises an improved pre-charge circuit for pre-charging a bit line during a pre-charge period to increase the speed of read operations. In another embodiment, a sense amplifier comprises simplified address decoding circuitry to increase the speed of read operations.

Sense amplifier with bit line pre-charge circuit for reading flash memory cells in an array

A system and method to inhibit the erasing of a portion of a sector of split gate flash memory cells while allowing the remainder of the sector to be erased is disclosed. The inhibiting is controlled by control logic that applies one or more bias voltages to the portion of the sector whose erasure is to be inhibited.

System and method to inhibit erasing of portion of sector of split gate flash memory cells

A memory device that includes a plurality of ROM cells each having spaced apart source and drain regions formed in a substrate with a channel region therebetween, a first gate disposed over and insulated from a first portion of the channel region, a second gate disposed over and insulated from a second portion of the channel region, and a conductive line extending over the plurality of ROM cells. The conductive line is electrically coupled to the drain regions of a first subgroup of the ROM cells, and is not electrically coupled to the drain regions of a second subgroup of the ROM cells. Alternately, a first subgroup of the ROM cells each includes a higher voltage threshold implant region in the channel region, whereas a second subgroup of the ROM cells each lack any higher voltage threshold implant region in the channel region.

Array of non-volatile memory cells with ROM cells

The present invention relates to a flash memory device that uses dummy memory cells as source line pull down circuits. In one embodiment, when a memory cell is in read mode or erase mode, its source line is coupled to ground through a bitline of a dummy memory cell, which in turn is coupled to ground. When the memory cell is in program mode, the bitline of the dummy memory cell is coupled to an inhibit voltage, which places the dummy memory cell in a program inhibit mode that maintains the dummy memory cell in erased state.

Flash memory system using memory cell as source line pull down circuit

A non-volatile memory device with a current injection sensing amplifier is disclosed.

Non-volatile memory device with current injection sensing amplifier

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Shanghai, China

Ning Bai