Infineon Technologies Flash Gmbh & Co. Kg

Nimrod Ben-Ari

Giacomo Curatolo

Rico Srowik

Marco Goetz

Marco Götz

Ifat Nitzan

A memory device architecture having improved bitline pre-charge and wordline timing operations includes a pre-charge driver, a pre-charge line, a timing controller, a wordline driver, and a wordline coupled to a selected memory cell. The pre-charge driver is operable to supply a pre-charge signal to a pre-charge line when activated by the pre-charge triggering signal. The pre-charge line is operable to supply a pre-charge output signal. The timing controller is coupled to receive the pre-charge output signal, and based thereon, provide a wordline triggering signal. The wordline triggering signal is supplied to the wordline driver, which applies a wordline signal to the selected memory cell.

Memory device architecture and method for improved bitline pre-charge and wordline timing

A semiconductor memory device (M) includes a memory array (MA) having a plurality of memory cells, a redundancy array (RA) having a plurality of memory cells, a non-volatile redundancy information memory (NVR) having a plurality of memory cells for storing redundancy information, and a redundancy control unit (RU) for selecting either memory cells in the memory array (MA) or memory cells in the redundancy array (RA). In one example, the non-volatile redundancy information memory (NVR) is connected directly to the redundancy control unit (RU) by means of at least one sense amplifier (SA).

Semiconductor memory device having a redundancy information memory directly connected to a redundancy control circuit

A method and arrangement are provided for programming an electrically erasable programmable read-only memory cell capable of storing at least one information bit. The memory cell has a charge-trapping region. According to the invention, during a first period of time, a fixed voltage is applied to the memory cell to inject and store electrical charge in the charge-trapping region. This period of time is followed by second period of time during which a constant current is applied to the memory cell to complete the programming step. By monitoring a change in voltage during the second period of time, a monitoring of a resulting threshold voltage is possible directly during programming.

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Natanya, Israel

Nimrod Ben-Ari