Intel Corporation

Nimrod Angel

Alexander Gendler

Ankush Varma

Nir Rosenzweig

Arik Gihon

Efraim Rotem

Krishnakanth Venkata Sistla

Alexander Uan-Zo-Li

Michael Zelikson

Alexander Lyakhov

Ameya Ambardekar

Ido Melamed

Tamir Salus

Rachid Rayess

Eliezer Weissmann

Stephen H Gunther

Fabrice Paillet

Avinash N Ananthakrishnan

Nadav Shulman

Eugene Gorbatov

Vivek Garg

Harish Krishnamurthy

Tod F Schiff

Chee Lim Nge

Anant S Deval

Shaun M Conrad

Yoni Aizik

Amit Kumar Jain

Sameer Shekhar

Tomer Ziv

Esfir Natanzon

Sapumal Wijeratne

Philip R Lehwalder

Ariel Szapiro

Christopher J Lake

Khondker Z Ahmed

Yevgeni Sabin

Adwait Purandare

Sergio Carlo Rodriguez

Hem Doshi

Patrick K Leung

Arye Albahari

Elkana Korem

Eric Dehaemer

Yoav Ben-Raphael

Nir Misgav

Vishram Shriram Pandit

Chen Ranel

Natanel Abitan

Vikas Vij

Reena Patel

Vijay Degalahal

Rachid E Rayess

Techniques and mechanisms for transparently transitioning an interconnect fabric between a first frequency and a second frequency. In an embodiment, the fabric is coupled to an end point device via an asynchronous device. One or more nodes of the fabric operate in a first clock domain based on a clock signal, while the end point device operates in a different clock domain. Controller circuitry changes a frequency of the clock signal by stalling the clock signal throughout a first period of time which is greater than a duration of three cycles of a lower one of the first frequency or the second frequency. After the first period of time, cycling of the clock signal is provided at the second frequency. In another embodiment, the asynchronous device enables the frequency change without preventing communication with the end point device.

Device, method and system for transparently changing a frequency of an interconnect fabric

A local power control arbiter is provided to interface with a global power control unit of a processing platform having a plurality of processing entities. The local power control arbiter controls a local processing unit of the processing platform. The local power arbiter has an interface to receive from the global power control unit, a local performance limit allocated to the local processing unit depending on a global power control evaluation and processing circuitry to determine any change to one or more processing conditions prevailing in the local processing unit on a timescale shorter than a duration for which the local performance limit is applied to the local processing unit by the global power control unit and to select a performance level for the local processing unit depending on both the local performance limit and the determined change, if any, to the prevailing processing conditions on the local processing unit.

Power control arbitration

In one embodiment, an apparatus comprises: a plurality of intellectual property (IP) circuits, each of the plurality of IP circuits including a configuration register to store a dynamic current budget; and a power controller coupled to the plurality of IP circuits, the power controller including a dynamic current sharing control circuit to receive current throttling hint information regarding a workload to be executed on at least some of the plurality of IP circuits and generate the dynamic current budget for each of the plurality of IP circuits based at least in part thereon. Other embodiments are described and claimed.

System, apparatus and method for dynamically controlling current consumption of processing circuits of a processor

Described is an apparatus and method to prevent a processor from abruptly shutting down by proactive power management. The apparatus comprises a power supply rail to receive a current and a voltage from a power supply generator (e.g., a DC-DC converter, and low dropout regulator); a processor coupled to the power supply rail, wherein the processor is to operate with a current and a voltage provided by the power supply rail; and an interface to receive a request to throttle one or more performance parameters of the processor when a monitored current through the power supply rail or a monitored voltage on the power supply rail crosses a threshold current or a threshold voltage, respectively, wherein the threshold current is below a catastrophic threshold current of a voltage regulator, or wherein the threshold voltage is above a catastrophic threshold voltage of the processor.

Apparatus and method for proactive power management to avoid unintentional processor shutdown

A power supply architecture combines the benefits of a traditional single stage power delivery, when there are no additional power losses in the integrated VR with low VID and low CPU losses of FIVR (fully integrated voltage regulator) and D-LVR (digital linear voltage regulator). The D-LVR is not in series with the main power flow, but in parallel. By placing the digital-LVR in parallel to a primary VR (e.g., motherboard VR), the CPU VID is lowered and the processor core power consumption is lowered. The power supply architecture reduces the guard band for input power supply level, thereby reducing the overall power consumption because the motherboard VR specifications can be relaxed, saving cost and power. The power supply architecture drastically increases the CPU performance at a small extra cost for the silicon and low complexity of tuning.

Digital linear regulator clamping method and apparatus

A dedicated pin of a processor or system-on-chip (SoC) is used to indicate whether power level (e.g., charge, voltage, and/or current) of a battery falls below a threshold. The threshold can be predetermined or programmable. The battery is used to provide power to the processor and/or SoC. Upon determining that the power level of the battery falls below the threshold, the processor by-passes the conventional process of entering low performance or power mode, and directly throttles voltage and/or operating frequency of the processor. This allows the processor to continue to operate at low battery power. The fast transition (e.g., approximately 10 &#x3bc;S) from an active state to a low performance or power mode, in accordance with a logic level of the voltage on the dedicated pin, reduces decoupling capacitor design requirements, and makes it possible for the processor to adapt higher package power control settings (e.g., PL4).

Fast dynamic capacitance, frequency, and/or voltage throttling apparatus and method

Various embodiments provide a voltage regulator circuit with automatic phase shedding. A control circuit may control first transitions of a power state of the voltage regulator based on an average current draw of the voltage regulator. The control circuit may further control second transitions of the power state of the voltage regulator based on a voltage droop of the output voltage and/or a peak current draw of the voltage regulator. The first transitions may be performed synchronously, and the second transitions may be performed asynchronously. Other embodiments may be described and claimed.

Autonomous phase shedding control for a voltage regulator

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Nimrod Angel