Arm Limited

Nimish Sharma

Bo Zheng

Lalit Gupta

Fakhruddin Ali Bohra

El Mehdi Boujamaa

Nicolaas Klarinus Johannes Van Winkelhoff

Hetansh Pareshbhai Shah

Ankur Goel

Ishita Satishchandra Desai

Vikash Kumar

Nitesh Gautam

Ishan Khera

Various implementations described herein refer to a method for providing memory with one or more banks. The method may include coupling read-write column multiplexer circuitry to the memory via bitlines including coupling a write column multiplexer to the bitlines for write operations and coupling a read column multiplexer to the bitlines for read operations. The method may include performing concurrent read operations and write operations in the one or more banks of the memory with the write column multiplexer and the read column multiplexer via the bitlines.

Concurrent memory access operations

In a particular implementation, a circuit comprises: a memory array including a plurality of bit cells, where each of the bit cells are coupled to a respective bit path; a first multiplexer comprising a plurality of column address locations, where each of the plurality of column address locations is coupled to the memory array and corresponds to a respective bit path capacitance; and a variable capacitance circuit coupled to a reference path and configured to substantially match reference path capacitance to each of the respective bit path capacitances.

Circuits and methods for capacitor modulation

Various implementations described herein are directed to a device having memory circuitry with a core array of bitcells. The device may include write assist circuitry having passgates coupled to the bitcells via bitlines. The passgates may include a first passgate coupled to the bitcells via a first bitline and a second passgate coupled to the bitcells via a second bitline, and a gate of the second passgate may be coupled to the first bitline.

Write assist circuitry

The claimed subject matter relate to circuits and/or methods, which operate to introduce a variable delay in a write-assist signal to a write driver of an array of SRAM cells. Particularly, a variable delay may be introduced by way of a voltage tracking circuit, which may generate a trigger signal in response to a voltage signal from an array of access devices that replicate access devices of the array of SRAM cells.

Memory cell write assist in response to voltage tracking of a replica circuit

Growing community of inventors

Jalandhar, India

Nimish Sharma