Cavium, Inc.

Marvell Asia Pte., Ltd.

Xpliant, Inc.

Nimalan Siva

Saurin Patel

Mohan Balan

Keqin Han

Weihuang Wang

Tsahi Daniel

Harish Krishnamoorthy

Kishore Badari Atreya

Zubin Shah

Ankit Anand

Gerald Schmidt

Anh T Tran

Premshanth Theivendran

Soumya Gollamudi

Nikita Goyal

Pratik Shah

Polasanapalli Sri Devi

Vadana Desai

Sri Devi Polasanapalli

A new approach of systems and methods to support automatic generation of multiple platform-dependent instruction sets from a single specification of an integrated circuit (IC). First, a specification compiler accepts as input a first instruction set of a plurality of first instructions in a specification format, wherein the first instruction set defines a design pattern of one or more specifications and/or requirements of the IC and is independent of any implementation or platform of the IC. The design tool then converts the first instruction set into a second instruction set of a plurality of second instructions in an intermediate format. A language compiler then accepts and compiles the second instruction set into a plurality of third instruction sets, wherein each of the plurality of third instruction sets comprises a plurality of third instructions in a specific language for a specific platform targeting a specific implementation or application of the IC.

System and method for generating multiple platform-dependent instruction sets from single hardware specification

A new approach is proposed to support device under test (DUT) validation reuse across a plurality of platforms, e.g., hardware simulation, hardware emulation, and post-silicon validation. First, an inference profile used for an inference operation of an application, e.g., a machine learning (ML) application, is generated based on a set of profile configurations, a set of test parameters, and a set of randomized constraints. A plurality of math functions specified by, e.g., an architecture team, for the ML application are also statically and/or dynamically verified via block simulation and/or formal verification. An inference model for the DUT is then built based on the inference profile and the plurality of verified math functions. Finally, an inference database including one or more of stimulus, DUT configurations, input data and predicted output results is generated based on the inference model, wherein the inference database for the DUT is reusable across the plurality of platforms.

System and method for device under test (DUT) validation reuse across multiple platforms

A software and hardware co-validation for SDN SoC method and system are able to be used to test software and hardware using PCIe (or another implementation) utilizing sockets and messages as the communication medium. An entire software stack as well as hardware are able to be tested. Additionally, multiple chips (SoCs) are able to be programmed at the same time, not just one, as in previous implementations.

Software assisted hardware configuration for software defined network system-on-chip

A testbench for testing a device under test (DUT), wherein the testbench has a verification environment including a reference model, a scoreboard and a customized agent for each interface that the DUT needs to receive input from and/or transmit output on. The testbench system is able to be generated by a testbench builder that automatically creates a scoreboard, a reference model, a dispatcher and generic agents including generic drivers, loopback ports, sequencers and/or generic monitors for each interface and then automatically customize the generic agents based on their corresponding interface such that the agents meet the requirements of the interface for the DUT.

Testbench builder, system, device and method

A testbench, including a verification environment, tests a device under test (DUT). A packet tracking module, which is verification environment agnostic, is configured to track packets in the verification environment. The packet tracking module maintains an associative data structure of packet identifiers that are indexed by a unique value, a counter for identifying the packets in the verification environment, and a set of routines for tracking the packets in the verification environment during different stages of the testing.

Packet tracking in a verification environment

Testbench builder, system, device and method including latency detection

Testbench builder, system, device and method having agent loopback functionality

A network switch includes a memory configurable to store alternate table representations of an individual trie in a hierarchy of tries. A prefix table processor accesses in parallel, using an input network address, the alternate table representations of the individual trie and searches for a longest prefix match in each alternate table representation to obtain local prefix matches. The longest prefix match from the local prefix matches is selected. The longest prefix match has an associated next hop index base address and offset value. A next hop index processor accesses a next hop index table in the memory utilizing the next hop index base address and offset value to obtain a next hop table pointer. A next hop processor accesses a next hop table in the memory using the next hop table pointer to obtain a destination network address.

Apparatus and method for processing alternately configured longest prefix match tables

Embodiments of the present invention relate to a scalable interconnection scheme of multiple processing engines on a single chip using on-chip configurable routers. The interconnection scheme supports unicast and multicast routing of data packets communicated by the processing engines. Each on-chip configurable router includes routing tables that are programmable by software, and is configured to correctly deliver incoming data packets to its output ports in a fair and deadlock-free manner. In particular, each output port of the on-chip configurable routers includes an output port arbiter to avoid deadlocks when there are contentions at output ports of the on-chip configurable routers and to guarantee fairness in delivery among transferred data packets.

Matrix of on-chip routers interconnecting a plurality of processing engines and a method of routing using thereof

Testbench builder, system, device and method with phase synchronization

Testbench builder, system, device and method including a generic monitor and transporter

A co-verification method and system are described herein. The co-verification method is able to verify software and hardware at the same time. Constraints are provided to a software compiler which generates programming values. The programming values and stimulus from a verification test bench are utilized to test a design such as a microprocessor.

Co-verification&#x2014;of hardware and software, a unified approach in verification

Testbench builder, system, device and method including a dispatcher

A network switch includes packet processing units in a first processor core. An interface module is connected to the packet processing units. The interface module supports a unified table search request interface and a unified table search response interface. A common memory pool is connected to the interface module. The common memory pool includes a variety of memory types configurable to support multiple parallel table search requests.

Apparatus and method for table search with centralized memory pool in a network switch

Growing community of inventors

San Ramon, CA, United States of America

Nimalan Siva