Texas Instruments Corporation

Nima Shahidi

Jaimal Mallory Williamson

Jose Carlos Arroyo

Yaoyu Pang

An assembly () comprising a semiconductor device () with solderable bumps (); a substrate () with a layer () of a first insulating compound and an underlying metal layer () patterned in contact pads () and connecting traces (), the insulating layer having openings () to expose the surface () and sidewalls () of underlying traces; the device bumps soldered onto the contact pads, establishing a gap () between device and top insulating layer; and a second insulating compound () cohesively filling the gap and the second openings, thereby touching the underlying traces, the second insulating compound having a higher glass transition temperature, a higher modulus, and a lower coefficient of thermal expansion than the first insulating compound.

Semiconductor substrate having stress-absorbing surface layer

An integrated circuit (IC) package, device, including a substrate having a top surface with an IC die mounting area and a peripheral area surrounding the mounting area, a plurality of parallel conductor layers, a plurality of insulating layers and a plurality of plated through holes (PTHs) extending through the conductor layers and insulating layers. Various substrate structures in which certain of the PTHs and/or conductor layers and/or insulating layers have different CTE's than the others is disclosed. The various structures may reduce circuit failures due to substrate warpage and/or solder joint damage associated with a CTE mismatch between the substrate and the IC die.

Integrated circuit package and method of manufacture

An electronic assembly includes a copper pillar attach substrate that has a dielectric layer and a solder resist layer overlying the dielectric layer. The solder resist layer has a plurality of solder resist openings. A plurality of parallel traces are formed on the dielectric layer. Each trace has a first end portion, a second end portion and an intermediate portion. The first and second end portions of each trace are covered by the solder resist layer and the intermediate portions are positioned in the solder resist openings. Each of the intermediate portions has at least one conductive coating layer on it and has a height measured from the dielectric layer to the top of the topmost conductive coating layer that is at least as great as the solder resist layer thickness.

Growing community of inventors

Dallas, TX, United States of America

Nima Shahidi