Ati Technologies Ulc

Advanced Micro Devices Corporation

Ati Technologies Inc.

Nima Osqueizadeh

Gamal Refai-Ahmed

Salim Lakhani

Eric D Meyer

Paul Blinzer

Robert A Wiley

Xiaohua H Sun

Jim E Loro

A Mei Lan Shepherd-Murray

Ross Lau

Steven Chan

A reporting device communicates with a master device by a first component and a daisy-chained second component. The reporting device receives a signal from the master device via the first component. The signal triggers the reporting device to transmit synchronously a telemetry data packet on the daisy-chained second component when a downstream device is coupled to the second component. The reporting device receives a first header packet having an address of the reporting device, transmits the telemetry data packet to the downstream device, and transmits a second header packet having an address of the downstream device.

Slave-to-master data and out-of-sequence acknowledgements on a daisy-chained bus

Described herein is a method and system for directly accessing and transferring data between a first memory architecture and a second memory architecture associated with a graphics processing unit (GPU) by treating the first memory architecture, the second memory architecture and system memory as a single physical memory, where the first memory architecture is a non-volatile memory (NVM) and the second memory architecture is a local memory. Upon accessing a virtual address (VA) range by a processor, the requested content is paged in from the single physical memory and is then redirected by a virtual storage driver to the second memory architecture or the system memory, depending on which of the GPU or CPU triggered the access request. The memory transfer occurs without awareness of the application and the operating system.

Method and apparatus for integration of non-volatile memory

Described herein are a method and device for transferring data in a computer system. The device includes a host processor, a plurality of first memory architectures, a switch, a redundant array of independent drives (RAID) assist unit; and a second memory architecture. The host processor is configured to send a data transfer command to the RAID assist unit via the switch. The RAID assist unit is configured to create a set of parallel memory transactions between the plurality of first memory architectures and the second memory architecture, execute the set of parallel memory transactions via the local switch and absent interaction with the host processor; and notify the host processor upon completion of data transfer. In an implementation, the plurality of first memory architectures is non-volatile memories (NVMs) and the second memory architecture is local memory.

Apparatus for connecting non-volatile memory locally to a GPU through a local switch

Described is a solid state graphics (SSG) subsystem including a die and a package, where the die includes a memory hub, graphics processing unit(s) (GPU(s)) connected to the memory hub, first memory architecture controller(s) connected to the memory hub and directly controlling access to first memory architecture(s), second memory architecture controller associated with each GPU and each second memory architecture controller connected to the memory hub and second memory architecture(s), an expansion bus first memory architecture controller connected to the memory hub and being an endpoint for a host system and an expansion bus controller coupled to the expansion bus first memory architecture controller and capable of connecting to the host system. The first memory architecture(s) and the second memory architecture(s) are either located on the SSG subsystem, located on the package, or a combination thereof.

System on chip having integrated solid state graphics controllers

Described herein are apparatus for connecting a first memory architecture locally to a graphics processing unit (GPU) through a local switch, where the first memory architecture can be a non-volatile memory (NVM) or other similarly used memories, for example, along with associated controllers. The apparatus includes the GPU(s) or discrete GPU(s) (dGPU(s)) (collectively GPU(s)), second memory architectures associated with the GPU(s), the local switch, first memory architecture(s), first memory architecture controllers or first memory architecture connector(s). In an implementation, the local switch is part of the GPU. The apparatus can also include a controller for distributing a large transaction among multiple first memory architectures. In an implementation, the first memory architectures can be directly connected to the GPU. In an implementation, the apparatus is user configurable. In an implementation, the apparatus is a solid state graphics (SSG) card.

A device to thermally couple a thermal management apparatus to at least one heat generating component of a circuit substrate includes at least a first portion that is adapted to couple to the thermal management apparatus, and at least a second portion that is adapted to couple to the thermal management apparatus. The first portion and the second portion may be symmetrically arranged relative to each other. The first portion and the second portion are adapted to thermally couple the thermal management apparatus to the heat generating component with a first spring bias. The first portion and the second portion are further adapted to maintain the thermal management apparatus thermally coupled to the heat generating component with a second spring bias.

Variable spring rate thermal management apparatus attachment mechanism

The present disclosure relates to a thermal management apparatus used to manage temperature of components mounted to a circuit substrate, such as electronic or optical components. The apparatus includes a heat dissipation structure that includes at least one protrusion extending from a surface of the heat dissipation structure. A carrier structure is also included and engages with the heat dissipation structure. The carrier structure includes an aperture that receives the at least one protrusion. Additionally, the apparatus includes at least one biasing structure that is configured to allow movement of the heat dissipation structure relative to the carrier structure and provides a biasing force tending to move the heat dissipation structure and carrier structure together.

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Markham, Canada

Nima Osqueizadeh