Infineon Technologies Ag

Nils Jensen

Andreas Peter Meiser

Marie Denison

Gerhard Prechtl

An integrated circuit is disclosed having a semiconductor component comprising a first p-type region and a first n-type region adjoining the first p-type region, which together form a first pn junction having a breakdown voltage. A further n-type region adjoining the first p-type region or a further p-type region adjoining the first n-type region is provided, the first p-type or n-type region and the further n-type or p-type region adjoining the latter together forming a further pn junction having a further breakdown voltage, the first pn junction and the further pn junction being connected or connectable to one another in such a way that, in the case of an overloading of the semiconductor component, on account of a current loading of the first pn junction, first of all the further pn junction breaks down.

Integrated circuit

An integrated circuit includes a semiconductor body of a first conductivity type. The semiconductor body includes a first semiconductor zone of a second conductivity type opposite the first conductivity type. The first semiconductor zone extends to a surface of the semiconductor body. A second semiconductor zone of the first conductivity type is embedded in the first semiconductor zone and extends as far as the surface. A third semiconductor zone of the second conductivity type at least partly projects from the first semiconductor zone along a lateral direction running parallel to the surface. A contact structure provides an electrical contact with the first and second semiconductor zones at the surface. The second semiconductor zone is arranged, along the lateral direction, between the part of the third semiconductor zone which projects from the first semiconductor zone and a part of the contact structure in contact with the first semiconductor zone.

Integrated circuit with ESD structure

The invention relates to an integrated circuit having a semiconductor component () comprising a first p-type region () and a first n-type region () adjoining the first p-type region (), which together form a first pn junction having a breakdown voltage. According to the invention, a further n-type region adjoining the first p-type region or a further p-type region () adjoining the first n-type region () is provided, the first p-type or n-type region () and the further n-type or p-type region () adjoining the latter together forming a further pn junction having a further breakdown voltage, the first pn junction and the further pn junction being connected or connectable to one another in such a way that, in the case of an overloading of the semiconductor component, on account of a current loading of the first pn junction, first of all the further pn junction breaks down.

An integrated semiconductor diode arrangement is provided. The arrangement includes an anode region and a cathode region that are formed in a semiconductor material region. The anode region has an arrangement of alternately occurring and directly adjacent first and second anode zones, which alternate in their conductivity type. The anode region furthermore has a first particular anode zone of the second conductivity type, the lateral extent of which is comparatively larger than that of the further anode zones of the same conductivity type.

Integrated semiconductor diode arrangement and integrated semiconductor component

A diode structure having high ESD stability is described. Other embodiments provide an integral power switching arrangement having an integrated low leakage diode.

Diode structure and integral power switching arrangement

An ESD protection structure for protecting an integrated circuit from electrostatic discharge, having a bipolar protection element, whose emitter is formed by an emitter zone of the first conduction type, whose collector is formed by a buried layer of the first conduction type, and whose base is formed by a base zone of the second conduction type disposed in-between. The base zone is spaced apart from the buried layer by an intermediate layer. Highly and lightly doped regions alternatively are provided in a section of the buried layer. The highly doped regions are spaced apart from one another by the lightly doped regions. A region with a reduced breakdown voltage of the protection element is disposed in a part of the protection element spaced apart from the section of the buried layer. Also provided is an integrated circuit having such an ESD protection structure.

Growing community of inventors

Munich, Germany

Nils Jensen