Oracle America, Inc.

Sun Microsystems, Inc.

Oracle International Corporation

Nils Gura

Hans Eberle

Wladyslaw Olesinski

Lawrence Spracklen

Vipul Gupta

Guy Lewis Steele, Jr

Sumti Jairath

David R Chase

Robert Dickson

Aron J Silverton

Peter J Yakutis

Sheueling Chang-Shantz

Leonard D Rarick

Russell Allen Brown

Sheueling Chang Shantz

Edouard Goupy

Robert J Drost

Christopher Hans Olson

Gregory Frederick Grohoski

Robert David Hopkins

Neil C Wilhelm

Bernard Tourancheau

Hagen W Peters

Arvinderpal S Wander

Nicolas Fugier

Georgios A Passas

Andreas Mejia

Stephen C Fung

Douglas Stebila

Daniel Finchelstein

Marc Herbert

A hardware-implemented rate limiter is described. This implementation guarantees that messages containing a value v are not forwarded at a higher rate than a predefined threshold value r. More specifically, given a number of times x in a time interval y, which specifies a rate r defined by x/y, the rate limiter reports a violation by selectively setting an error value when v occurs more than x times during the time interval y. Moreover, the rate limiter may be able to keep track of multiple predefined threshold values for different rates. Furthermore, the rate limiter may keep track of 2different values v, where b is the number of digits of the binary representation of v.

Rate limiter for a message gateway

Hardware circuitry may evaluate minimal perfect hash functions mapping keys to addresses in lookup tables. The circuitry may include primary hash function sub-circuits that apply linear hash functions to input key values (using carry-free arithmetic) to produce primary hash values. Each sub-circuit may multiply bit vectors representing key values by a bit matrix and add a constant bit vector to the result. The circuitry may include a secondary hash function sub-circuit that generates secondary hash values by aggregating values associated with multiple primary hash values using signed, unsigned, or modular integer addition, or bit-wise XOR operations. Secondary hash values may be usable to access data values in the lookup table that are associated with particular input key values. The circuitry may determine the validity of input keys and may alter the configuration or contents of the lookup tables. The hash function sub-circuits may include programmable hash tables.

Systems and methods for implementing dynamically configurable perfect hash tables

A lookup circuit evaluates hash functions that map keys to addresses in lookup tables. The circuit may include multiple hash function sub-circuits, each of which applies a respective hash function to an input key value, producing a hash value. Each hash function sub-circuit (which may include a programmable hash table) may multiply bit vectors representing key values by a bit matrix and add a constant bit vector to the results. Each hash value may be used to access a location in a lookup table in memory to obtain its contents (e.g., a key and associated data). The circuit may include a selection sub-circuit that selects the data of one of the identified locations as an output of the lookup circuit (e.g., one whose key matches the input key). The circuit may modify obtained data prior to its selection and may output a signal indicating the validity of input keys.

Systems and methods for implementing low-latency lookup circuits using multiple hash functions

A lookup circuit evaluates hash functions that map keys to addresses in lookup tables. The circuit includes multiple hash function sub-circuits, each of which applies a respective hash function to an input key, producing a hash value. Candidate pairs of hash functions to be implemented by the hash function sub-circuits (or hash function bit matrices thereof) may be generated and tested for suitability in hashing a particular collection of keys. Each hash function bit matrix may be generated according to heuristics chosen to improve the likelihood that it will be suitable for use in a pair, and may be tested against previously generated hash function bit matrices contained in one or more pools (each of which may contain matrices generated using different heuristics) to identify suitable pairs. The hash function bit matrices may be represented in the pools in a tabulated form, which may reduce the suitability testing time.

Systems and methods for rapidly generating suitable pairs of hash functions

Embodiments of a system that includes a switch and a buffer-management technique for storing signals in the system are described. In this system, data cells are dynamically assigned from a host buffer to at least a subset of switch-ingress buffers in the switch based at least in part on the occupancy of the switch-ingress buffers. This buffer-management technique may reduce the number of switch-ingress buffers relative to the number of input and output ports to the switch, which in turn may overcome the limitations posed by the amount of memory available on chips, thereby facilitating large switches.

Dynamic assignment of data to switch-ingress buffers

Techniques are disclosed relating to a processor including instruction support for performing a Montgomery multiplication. The processor may issue, for execution, programmer-selectable instruction from a defined instruction set architecture (ISA). The processor may include an instruction execution unit configured to receive instructions including a first instance of a Montgomery-multiply instruction defined within the ISA. The Montgomery-multiply instruction is executable by the processor to operate on at least operands A, B, and N residing in respective portions of a general-purpose register file of the processor, where at least one of operands A, B, N spans at least two registers of general-purpose register file. The instruction execution unit is configured to calculate P mod N in response to receiving the first instance of the Montgomery-multiply instruction, where P is the product of at least operand A, operand B, and R^&#x2212;1.

Instruction support for performing montgomery multiplication

A secure end to end connection is established between a remote device having a wireless link and a control/monitoring location for the remote device through a gateway. During the establishing of the secure connection, a compressed message representation is used to communicate between the gateway and the remote device over the wireless link and an uncompressed message representation is used to communicate between the gateway and the first location. The establishment of the secure connection utilizes public-key algorithms.

Method and apparatus for reducing bandwidth usage in secure transactions

A method for transmitting packets, including forwarding a first set of upstream packets and a first set of local packets by inserting at least one of the first set of local packets between subsets of the first set of upstream packets according to a first insertion rate; calculating a second insertion rate after forwarding a predetermined number of upstream packets generated by a single upstream source, by dividing a cardinality of the first set of upstream packets by a greatest common divisor of the predetermined number and the cardinality of the first set of upstream packets; and forwarding a second set of upstream packets and a second set of local packets from the local switch to the downstream switch by inserting at least one of the second set of local packets between subsets of the second set of upstream packets according to the second insertion rate.

Simple fairness protocols for daisy chain interconnects

In response to executing an arithmetic instruction, a first number is multiplied by a second number, and a partial result from a previously executed single arithmetic instruction is fed back from a first carry save adder structure generating high order bits of the current arithmetic instruction to a second carry save adder tree structure being utilized to generate low order bits of the current arithmetic instruction to generate a result that represents the first number multiplied by the second number summed with the high order bits from the previously executed arithmetic instruction. Execution of the arithmetic instruction may instead generate a result that represents the first number multiplied by the second number summed with the partial result and also summed with a third number, the third number being fed to the carry save adder tree structure.

Method and apparatus for implementing processor instructions for accelerating public-key cryptography

In response to executing a single arithmetic instruction, a first number is multiplied by a second number, and a partial result from a previously executed single arithmetic instruction is added implicitly to generate a result that represents the first number multiplied by the second number summed with the partial result from a previously executed single arithmetic instruction. The high order portion of the generated result is saved in an extended carry register as a next partial result for use with execution of a subsequent single arithmetic instruction. Execution of a single arithmetic instruction may instead generate a result that represents the first number multiplied by the second number summed with the partial result and also summed with a third number.

Multiple multicast acknowledgements can be merged into a single multicast acknowledgement, thus reducing traffic and reducing logic complexity. An intermediate node that receives multiple multicast acknowledgements merges the multiple acknowledgements into a single acknowledgement, and then supplies the single merged acknowledgment to the multicast source. Encoding of the single merged acknowledgement conveys to the source which of the multicast targets successfully received (or which failed to receive) the multicast information.

Reliable multicast using merged acknowledgements

Modular multiplication of two elements X(t) and Y(t), over GF(2), where m is a field degree, may utilize field degree to determine, at least in part, the number of iterations. An extra shift operation may be employed when the number of iterations is reduced. Modular multiplication of two elements X(t) and Y(t), over GF(2), may include a shared reduction circuit utilized during multiplication and reduction. In addition, a modular multiplication of binary polynomials X(t) and Y(t), over GF(2), may utilize the Karatsuba algorithm, e.g., by recursively splitting up a multiplication into smaller operands determined according to the Karatsuba algorithm.

Modular multiplier

Embodiments of the present invention provide a system that schedules the transfer of cells in a switch. The system starts by receiving a set of cells to be transferred from a set of inputs of the switch to a set of outputs of the switch. The system includes S subschedulers, wherein each subscheduler processes N scheduling waves in sequence to generate a conflict-free transfer schedule for a given time slot for a matrix of transfer elements in the switch. The system then operates the subschedulers in parallel to generate S transfer schedules to transfer the cells from the set of inputs of the switch to the set of outputs of the switch during S time slots.

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Mountain View, CA, United States of America

Nils Gura