Xilinx, Inc.

Niloy Roy

Bradley K Fross

Siddharth Rele

Riyas Noorudeen Remla

Heera Nand

Mahesh Sankroj

Michael E Peattie

Kapil Usgaonkar

Adithya Balaji Boda

Rajesh Bansal

Vishal Kumar Vangala

Shashank Konanki

Vinaykumar Chepoori

Jake Chang

A connectivity tool validates a connectivity configuration of each manager of a plurality of managers in a system-on-chip (SoC) architecture based on data that indicate excluded interfaces of a plurality of interfaces of the SoC architecture and excluded subordinates of a plurality of subordinates of the SoC architecture. The connectivity configuration specifies a connectivity status of the manager and one or more of the plurality of interfaces. The connectivity tool configures connectivity paths of the SoC to include a path from a manager of the plurality of managers to a subordinate of the plurality of subordinates for each valid connectivity configuration.

Configuration of manager-subordinate connectivity paths of a system-on-chip

An integrated circuit includes a high-speed interface configured to communicate with a host system for debugging and a debug hub coupled to the high-speed interface. The debug hub is configured to receive a debug command from the host system as memory mapped data. The integrated circuit also includes a plurality of debug cores coupled to the debug hub. Each debug core is coupled to the debug hub by channels. The debug hub is configured to translate the debug command to a data stream and provide the data stream to a target debug core of the plurality of debug cores based on an address specified by the debug command.

High speed debug hub for debugging designs in an integrated circuit

Extracting transaction level information from an interface can include tracking transactions of an interface within an integrated circuit (IC) using a plurality of counters within the IC, wherein the counters generate counter data corresponding to the transactions. The method can include capturing signals of the interface as trace data for a trace window using an integrated logic analyzer within the IC, wherein a start of the trace window begins after a start of the tracking of the transactions using the plurality of counters. The method can also include using a host data processing system coupled to the IC, determining transaction level information for the interface using the counter data and the trace data for the trace window.

Extracting transaction level information from a circuit interface

Approaches for capturing states of signals of a circuit-under-test are disclosed. A logic analyzer circuit is coupled to the circuit-under-test and is configured to receive a plurality of probe signals and a plurality of trigger signals from the circuit-under-test. The logic analyzer circuit inputs data identifying a subset of the probe signals and a subset of the trigger signals. The logic analyzer circuit selects the subset of trigger signals for input to trigger logic and selects the subset of probe signals in the logic analyzer circuit after the logic analyzer circuit and the circuit-under-test are active. The logic analyzer circuit samples states of the subset of probe signals in response to the trigger logic and stores the sampled states of the subset of probe signals in a memory.

Configurable system and method for debugging a circuit

Various example implementations are directed to circuits and methods for debugging logic circuits utilizing a data bus for communication. According to an example implementation, an apparatus includes a logic circuit configured to communicate data over a data bus according to a communication protocol. The apparatus also includes a logic analyzer circuit coupled to the data bus. The logic analyzer circuit is configured to capture, in response to a control signal, samples of data signals communicated on the data bus. The logic analyzer circuit determines respective pairs of start and end positions of the data transactions in the captured samples. The logic analyzer circuit outputs the samples of the data signals and a set of metadata including the determined pairs of start and end positions of data transactions in the samples.

Methods and circuits for debugging data bus communications

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Hyderabad Telangana, India

Niloy Roy