3com Corporation

U.S. Ethernet Innovations, LLC

3 Com Corporation

Niles E Strohl

Glenn William Connery

Richard S Reid

Paul William Sherer

James P Rivers

Richard J Hausman

Cynthia Zikmund

Steven Paul Russell

Michael J Seaman

John H Hart

Jeffrey J Krause

Mark S Isfeld

Michael H Bowman

In a Local Area Network (LAN) system, an Ethernet adapter exchanges data with a host through programmed I/O (PIO) and FIFO buffers. The receive PIO employs a DMA ring buffer backup so incoming packets can be copied directly into host memory when the PIO FIFO buffer is full. The adapter may be programmed to generate early receive interrupts when only a portion of a packet has been received from the network, so as to decrease latency. The adapter may also be programmed to generate a second early interrupt so that the copying of a large packet to the host may overlap reception of the packet end. The adapter to begin packet transmission before the packet is completely transferred from the host to the adapter, which further reduces latency. The minimal latency of the adapter allows it to employ receive and transmit FIFO buffers which are small enough to be contained within RAM internal to an Application Specific Integrated Circuit (ASIC) containing the transceiver, ethernet controller, FIFO control circuitry and the host interface as well.

Programmed I/O ethernet adapter with early interrupts for accelerating data transfer

In a Local Area Network (LAN) system, an ethernet adapter exchanges data with a host through programmed I/O (PIO) and FIFO buffers. The receive PIO employs a DMA ring buffer backup so incoming packets can be copied directly into host memory when the PIO FIFO buffer is full. The adapter may be programmed to generate early receive interrupts when only a portion of a packet has been received from the network, so as to decrease latency. The adapter may also be programmed to generate a second early interrupt so that the copying of a large packet to the host may overlap reception of the packet end. The adapter to begin packet transmission before the packet is completely transferred from the host to the adapter, which further reduces latency. The minimal latency of the adapter allows it to employ receive and transmit FIFO buffers which are small enough to be contained within RAM internal to an Application Specific Integrated Circuit (ASIC) containing the transceiver, ethernet controller, FIFO control circuitry and the host interface as well.

Programmed I/O ethernet adapter with early interrupt and DMA control for

In a Local Area Network (LAN) system, an ethernet adapter exchanges data with a host through programmed I/O (PIO) and FIFO buffers. The receive PIO employs a DMA ring buffer backup so incoming packets can be copied directly into host memory when the PIO FIFO buffer is full. The adapter may be programmed to generate early receive interrupts when only a portion of a packet has been received from the network, so as to decrease latency. The adapter may also be programmed to generate a second early interrupt so that the copying of a large packet to the host may overlap reception of the packet end. The adapter may also be programmed to begin packet transmission before the packet is completely transferred from the host to the adapter, which further reduces latency. The minimal latency of the adapter allows it to employ receive and transmit FIFO buffers which are small enough to be contained within RAM internal to an Application Specific Integrated Circuit (ASIC) containing the transceiver, ethernet controller, FIFO control circuitry and the host interface as well.

Programmed I/O ethernet adapter with early interrupts for accelerating

DLL devices are built with multiple MAC address instead of a single MAC address, and provide a multiple virtual DLL interfaces to the upper layers (3-7) in a computer. This results in a new class of multi-function computers for attachment to a network system which take advantage of the multiple virtual DLL interfaces, to increase performance of the respective functions executed by the computer. Thus, a new network interface control apparatus and a new class of multi-function computer systems for attachments to networks are provided. The memory in the medium access control device stores a plurality of additional network addresses in addition to the assigned network addresses. The address filtering logic includes circuits responsive to the additional network addresses, such as logic for blocking a particular frame on at least one of the plurality of data channels when the source and destination address of a particular frame are found in the additional addresses stored in the memory. The plurality of data channels served by the media access control device may reside on a single physical interface, or in independent physical interfaces as suits the needs of a particular design. A high performance design would include independent buffering and queuing structures for each of the data channels. An alternative design may include shared buffering and queuing structures for a plurality of functional modules in the connected computer which have independent side network addresses.

Network station with multiple network addresses

Multifunction network station with network addresses for functional units

Apparatus for simulating a stack structure using a single register and a

A high performance bus suitable for high speed internetworking applications which is based on three bus phase types, including an arbitration phase, an address phase, and a data phase. The arbitration, address, and data phases share a single set of lines. Distributed arbitration logic on each of the interface devices supplies local arbitration codes to a particular line in the set of lines in the arbitration cycle, and detects an arbitration win during the same phase in response to the local arbitration code, and other arbitration codes driven on the set of lines during the arbitration cycle. Each module coupled to the bus also assigned a local priority code. During the arbitration cycle, both the arbitration code and the priority code are driven on respective subsets of the shared sets of lines. Assertion of the local priority code overrides normal requests for the bus. The arbitration logic on each module includes a bus request logic which has the effect of defining arbitration cycles, such that in a particular arbitration phase, a group of modules that asserts a bus request signal controls the bus request signal until all modules in the group have won arbitration.

Input/output bus architecture with parallel arbitration

In a computer system having a central processing unit which employs software drivers as part of a host for controlling peripheral units and including a bus for connecting with adapters for the peripheral units, wherein each adapter has distributed intelligence means for interpreting simple command information and a nonvolatile storage element for storing default configuration information, including a default port address for communication, a method is provided for configuring such intelligent adapters connected to the bus. The method includes initializing the intelligent adapters by applying power to the bus or by issuing a global reset signal and causing a driver to be loaded by the central processing unit so that the host broadcasts a start key via a sequence of write commands via the bus to any adapters on the bus and to elicit responses from the intelligent adapters in an interactive manner to narrow communication between the intelligent adapters and the host to a single intelligent adapter without first specifying a unique port address. The narrowing process involves causing the intelligent adapters to first rank themselves for communication with the host by referring to unique ordered value information, e.g., an identification serial number, stored in the nonvolatile storage element, such as an EEPROM element, placed on the adapter.

Method and apparatus for configuring a selected adapter unit on a common

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Tracy, CA, United States of America

Niles E Strohl