Intel Corporation

Nilay Mistry

Prasoonkumar Surti

Abhishek R Appu

Joydeep Ray

Altug Koker

Elmoustapha Ould-Ahmed-Vall

Subramaniam M Maiyuran

Vasanth Ranganathan

Varghese George

Ankur N Shah

Ben J Ashbaugh

Nicolas C Galoppo Von Borries

David M Puffer

Aravindh V Anantaraman

Selvakumar Panneer

Lakshminarayanan Striramassarma

Mike MacPherson

Valentin Andrei

Hema Chand Nalluri

Saurabh Tangri

David Puffer

An apparatus to facilitate a dynamically scalable and partitioned copy engine is disclosed. The apparatus includes a processor comprising copy engine hardware circuitry to facilitate copying surface data in memory and comprising: a plurality of copy front-end hardware circuitry to generate a plurality of surface data sub-blocks, wherein a number of the plurality of copy front-end hardware circuitry corresponds to a number of partitions configured for the processor, with each partition associated with a single copy front-end hardware circuitry; a plurality of copy back-end hardware circuitry to operate in parallel to process the plurality of surface data sub-blocks to perform memory accesses, wherein subsets of the plurality of copy back-end hardware circuitry are each associated with the single copy front-end hardware circuitry associated with each partition; and a connectivity matrix hardware circuitry to communicably connect the plurality of copy front-end hardware circuitry to the plurality of copy back-end hardware circuitry.

Dynamically scalable and partitioned copy engine

Multi-tile Memory Management for Detecting Cross Tile Access, Providing Multi-Tile Inference Scaling with multicasting of data via copy operation, and Providing Page Migration are disclosed herein. In one embodiment, a graphics processor for a multi-tile architecture includes a first graphics processing unit (GPU) having a memory and a memory controller, a second graphics processing unit (GPU) having a memory and a cross-GPU fabric to communicatively couple the first and second GPUs. The memory controller is configured to determine whether frequent cross tile memory accesses occur from the first GPU to the memory of the second GPU in the multi-GPU configuration and to send a message to initiate a data transfer mechanism when frequent cross tile memory accesses occur from the first GPU to the memory of the second GPU.

Multi-tile memory management for detecting cross tile access providing multi-tile inference scaling and providing page migration

An apparatus to facilitate copying surface data is disclosed. The apparatus includes copy engine hardware to receive a command to access surface data from a source location in memory to a destination location in the memory, divide the surface data into a plurality of surface data sub-blocks, process the surface data sub-blocks to calculate virtual addresses to which accesses to the memory are to be performed and perform the memory accesses.

Distributed copy engine

Growing community of inventors

Bengaluru, India

Nilay Mistry