Intel Corporation

Nilanjan Palit

Krishnakanth Venkata Sistla

Ankush Varma

Nikhil Gupta

Eliezer Weissmann

Eugene Gorbatov

Vasudevan Srinivasan

Abhinav Karhu

Andrew J Herdrich

Ioannis T Schoinas

Vivek Garg

Dean A Mulla

Robert P Adler

Nazar Syed Haider

Ripan Das

Adwait Purandare

Yogesh Bansal

Suresh Chemudupati

Aman Sewani

Eric Dehaemer

Boris Dolgunov

Rupal Parikh

Pavithra Sampath

Ujjwal Gupta

Nikethan Shivanand Baligar

Stanley Chen

Avishay Snir

Michael Tulanowski

Timothy Yee-Kwong Kam

Stephen Paul Haake

Ruirui Huang

Stephen Wang

Dorit Shapira

Shruthi Venugopal

Phani Kumar Kandula

Hierarchical Power Management (HPM) architecture considers the limits of scaling on a power management controller, the autonomy at each die, and provides a unified view of the package to a platform. At a simplest level, HPM architecture has a supervisor and one or more supervisee power management units (PMUs) that communicate via at least two different communication fabrics. Each PMU can behave as a supervisor for a number of supervisee PMUs in a particular domain. HPM addresses these needs for products that comprise a collection of dice with varying levels of power and thermal management capabilities and needs. HPM serves as a unified mechanism than can span collection of dice of varying capability and function, which together form a traditional system-on-chip (SoC). HPM provides a basis for managing power and thermals across a diverse set of dice.

Hierarchical power management apparatus and method

An apparatus and method for intelligently scheduling threads across a plurality of logical processors. For example, one embodiment of a processor comprises: a plurality of cores; one or more peripheral component interconnects to couple the plurality of cores to memory, and in response to a core configuration command to deactivate a core of the plurality of cores, a region within the memory is updated with an indication of deactivation of the core.

Apparatus and method for dynamic control of microprocessor configuration

An apparatus and method for intelligently scheduling threads across a plurality of logical processors. For example, one embodiment of a processor comprises: a plurality of cores to be allocated to form a first plurality of logical processors (LPs) to execute threads, wherein one or more logical processors (LPs) are to be associated with each core of the plurality of cores; scheduling guide circuitry to: monitor execution characteristics of the first plurality of LPs and the threads; generate a first plurality of LP rankings, each LP ranking including all or a subset of the plurality of LPs in a particular order; and store the first plurality of LP rankings in a memory to be provided to a scheduler, the scheduler to schedule the threads on the plurality of LPs using the first plurality of LP rankings; a power controller to execute power management code to perform power management operations including independently adjusting frequencies and/or voltages of one or more of the plurality of cores; wherein in response to a core configuration command to deactivate a first core of the plurality of cores, the power controller or privileged program code executed on the processor are to update the memory with an indication of deactivation of the first core, wherein responsive to the indication of deactivation of the first core, the scheduler is to modify the scheduling of the threads.

In one example, a semiconductor die includes a plurality of agents and a fabric coupled to at least some of the plurality of agents. The fabric may include at least one router to provide communication between two or more of the plurality of agents, the at least one router coupled to a first agent of the plurality of agents, where the first agent is to send a first message to the at least one router, the first message comprising a first header including a first source identifier, and the at least one router is to validate that the first source identifier is associated with the first agent and if so to direct the first message towards a destination agent, and otherwise to prevent the first message from being directed towards the destination agent. Other embodiments are described and claimed.

System, apparatus and method for tunneling validated security information

Growing community of inventors

Northborough, MA, United States of America

Nilanjan Palit