Samsung Electronics Co., Ltd.

Meta Platforms Technologies, LLC

Nilanjan Goswami

Steve John Clohset

Christopher James Goodman

Sushant Kondguli

David Conrad Tannenbaum

Michael Yee

Derek Lentz

Hideo Tamama

Eugene Gorbatov

Sonal Pinto

Swati Atrish

Kyle Durfee

Piyush Agarwal

Adithya Hrudhayan Krishnamurthy

Shanmathi Natarajan

A method includes receiving a source shape that is to be blended with a destination shape stored in a color buffer for an image; in response to determining that the source shape is associated with a blending mode that requires updates to pixels in the color buffer uncovered by the source shape: identifying empty tiles in the color buffer uncovered by the source shape and non-empty tiles in the color buffer covered by the source shape; for each of the empty tiles, sending instructions to clear pixel values associated with the empty tile in the color buffer; and for each of the non-empty tiles: identifying pixels of the non-empty tile that are covered by the destination shape but not the source shape; and sending instructions to clear pixel values associated with the pixels.

Destination update for blending modes in a graphics pipeline

A method is disclosed for receiving a synchronization signal from a display circuit configured to display a series of frames, each frame comprising a plurality of tiles of pixels, determining, based on the received synchronization signal, that the display circuit has consumed data corresponding to one or more tiles of a frame, identifying a predetermined number of tiles that are subsequent to the one or more tiles consumed by the display circuit based on the synchronization signal, determining that one or more tiles of the identified tiles require an update, selectively rendering the determined tiles, and transmitting the rendered tiles to the display circuit.

Partial rendering and tearing avoidance

In particular embodiments, a computing system of a device may determine a display peak power budget allocated for a display component of the device. The system may determine display information including display workload and display telemetry associated with the display component. The system may determine, in accordance with a display peak power management policy applied to the display peak power budget and the display information, one or more display-controlling parameters for maintaining the display component to operate within the display peak power budget. The system may determine, based on the one or more display-controlling parameters, a plurality of grayscales for a plurality of regions on a display screen of the device. The system may adjust a rendered frame based on the plurality of grayscales and output the adjusted rendered frame on the display screen of the device.

Display peak power management for artificial reality systems

A method includes receiving a block comprising pixels; encoding the pixels by: arranging the pixels in a sequence; generating a delta encoding of the pixels, the delta encoding comprising (a) a base value and (b) delta values having non-zero delta values and zero delta values, each delta value representing a difference between a corresponding pixel in the sequence and a previous pixel in the sequence; generating a symbol mask indicating whether each of the delta values is zero or non-zero; determining, based on magnitudes of the non-zero delta values, a symbol width for encoding each of the non-zero delta values; generating a sequence of symbols that respectively encode the non-zero delta values using the symbol width; generating a compression of the block by collating the symbol mask, the symbol width, and the sequence of symbols.

Low-power high throughput hardware decoder with random block access

A graphics pipeline of a graphics processing unit includes a compressor that receives one or more attributes (positional and non-positional) of a vertex that is output from a vertex shader. The compressor determines a format of the one or more attributes, and separates each attribute into parts based on the format of the attribute. The compressor compresses each respective part of the attribute based on a type of the part. The compressed parts of the attribute are stored in an attribute storage.

Efficient fast random access enabled geometry attribute compression mechanism

A method to process tiles of a screen space includes determining a tile-processing order for tiles of a first batch of primitives based on a tile-processing order for a second batch of primitives in which the second batch of primitives are processed prior to the first batch of primitives. The tiles of the first batch of primitives are processed based on the tile-processing order determined for the tiles of the first batch of primitives. The tile-processing order is updated as tiles of the first batch of primitives are pushed to a backend processing portion of a graphics processing unit. In one embodiment, determining the tile-processing order for the tiles of the first batch of primitives include arranging the tiles of the first batch of primitives that have a same screen-space as tiles of the second batch of primitives based on a most-recently-processed-tile-to-a-least-recently-processed tile order of the second batch of primitives.

Re-reference aware tile walk order for primitive binner

A system and a method are disclosed that reduce primitive overdraw in a GPU. An occlusion index (OI) for a first tile of a batch of graphical data. In one embodiment, the first tile is bypassed from an early coverage discard (ECD) first-in, first-out (FIFO) if the OI for the first tile is less than a first threshold, otherwise the first tile is entered into the ECD FIFO. The first tile is also bypassed from the ECD FIFO if the OI for the first tile is greater than a second threshold that is greater than the first threshold. In another embodiment, a queue length is logically changed for the first tile in the ECD FIFO if the OI for the first tile is greater than the first threshold and less than or equal to a third threshold that is greater than the first threshold and less than the second threshold.

Enhanced early coverage discard using opportunistic bypassing and dynamic queue resizing

A computer-implemented redundant-coverage discard method and apparatus for reducing pixel shader work in a tile-based graphics rendering pipeline is disclosed. A coverage block information (CBI) FIFO buffer is disposed within an early coverage discard (ECD) logic section. The FIFO buffer receives and buffers coverage blocks in FIFO order. At least one coverage block that matches the block position within the TCPM is updated. The TCPM stores per-pixel primitive coverage information. The FIFO buffer buffers a moving window of the coverage blocks. Incoming primitive information associated with the coverage blocks is compared with the per-pixel primitive coverage information stored in the tile coverage-primitive map (TCPM) table at the corresponding positions for the live coverages only. Any preceding overlapping coverage within the moving window of the coverage blocks is rejected. An alternate embodiment uses a doubly linked-list rather than a FIFO buffer.

Growing community of inventors

Livermore, CA, United States of America

Nilanjan Goswami