Intel Corporation

Other

Nikos Kaburlasos

Joydeep Ray

Abhishek R Appu

Travis T Schluessler

Jacek Kwiatkowski

Altug Koker

John H Feit

Prasoonkumar Surti

Balaji Vembu

Kamal Sinha

Sanjeev S Jahagirdar

Jonathan Kennedy

Bhushan M Borole

Elmoustapha Ould-Ahmed-Vall

Subramaniam M Maiyuran

Adam T Lake

Kiran Chand Veernapu

James M Holland

Wenyin Fu

Josh B Mastronarde

Philip R Laws

Eric C Samson

Vasanth Ranganathan

Michael Apodaca

Kai Xiao

Atsuo Kuwahara

Ankur N Shah

Jeffery S Boles

Louis Feng

Narayan Biswal

Devan Burke

Hugues Labbe

Eric J Asperheim

Karthik Vaidyanathan

Stanley J Baran

Gokcen Cilingir

Nilesh V Shah

Barnan Das

Archie Sharma

Mayuresh M Varerkar

Scott W Cheng

Guei-Yuan Lueh

Lidong Xu

Deepak Shashidhar Vembar

Tomer Bar-On

Abhishek Venkatesh

Chandrasekaran Sakthivel

Tomasz Janczak

David M Cimini

Peter L Doyle

Brent E Insko

Andrew T Lauritzen

Devon Worrell

Jill MacDonald Boyce

David M Puffer

Carsten Benthin

Eric J Hoekstra

Radhakrishnan Venkataraman

Jim Kardach

Murali Ramadoss

Linda L Hurd

Scott R Janus

Iqbal Rajwani

Sameer Kp

Slawomir Grajewski

Anupreet S Kalra

Christopher J Hughes

Gabor Liktor

John G Gierach

Xinmin Tian

Carson Brownlee

Sayan Lahiri

Jefferson Amstutz

Vivek Tiwari

Robert B Taylor

Durgaprasad Bilagi

Hong Jiang

Michael A Smith

Changliang Wang

Inder M Sodhi

Guy M Therien

Pattabhiraman K

James Little

Phani Kumar Kandula

Naveen Matam

David N Lombard

Eric J M Moret

Mark J Luckeroth

Sameer K P

Marc Beuchat

John Kelbert

Brad Bittel

Jaymin B Jasoliya

Hughes Labbe

Michael D Stoner

Lakshminarayan Jagannathan

Jlm Kardach

Jim Kardaeh

Vaishali Nikhade

Rodrigo De Oliveira Vivi

Embodiments described herein provided for an instruction and associated logic to enable a processing resource including a tensor accelerator to perform optimized computation of sparse submatrix operations. One embodiment provides a parallel processor comprising a processing cluster coupled with the cache memory. The processing cluster includes a plurality of multiprocessors coupled with a data interconnect, where a multiprocessor of the plurality of multiprocessors includes a tensor core configured to load tensor data and metadata associated with the tensor data from the cache memory, wherein the metadata indicates a first numerical transform applied to the tensor data, perform an inverse transform of the first numerical transform, perform a tensor operation on the tensor data after the inverse transform is performed, and write output of the tensor operation to a memory coupled with the processing cluster.

Systolic arithmetic on sparse data

Disclosed herein are embodiments of systems and methods for stable and elevated idle-mode temperature for assembled semiconductor devices. In an embodiment, a processor includes a communication interface configured to receive, from a first hardware component, instructions assigned to the processor for execution. The processor also includes temperature-measurement circuitry configured to monitor an on-chip temperature of the processor. The processor also includes control logic configured to: determine whether the processor is active or idle; determine whether the on-chip temperature of the processor exceeds a first threshold; based on determining that the processor is idle and that the on-chip temperature of the processor exceeds the first threshold, disable one or more idle-mode power-saving features of the processor; and selectively adjust one or more operating parameters of the processor to keep the on-chip temperature of the processor between the first threshold and a second (higher) threshold.

Systems and methods for stable and elevated idle-mode temperature for assembled semiconductor devices

An embodiment of an electronic processing system may include an application processor, persistent storage media communicatively coupled to the application processor, a graphics subsystem communicatively coupled to the application processor, a sense engine communicatively coupled to the graphics subsystem to provide sensed information, a focus engine communicatively coupled to the sense engine and the graphics subsystem to provide focus information, a motion engine communicatively coupled to the sense engine, the focus engine, and the graphics subsystem to provide motion information, and a motion biased foveated renderer communicatively coupled to the motion engine, the focus engine, the sense engine to adjust one or more parameters of the graphics subsystem based on one or more of the sense information, the focus information, and the motion information. Other embodiments are disclosed and claimed.

Motion biased foveated renderer

In an example, an apparatus comprises logic, at least partially comprising hardware logic, to receive an input from one or more detectors proximate a display to present an output from a graphics pipeline, determine that a user is not interacting with the display, and in response to a determination that the user is not interacting with the display, to reduce a frame rendering rate of the graphics pipeline. Other embodiments are also disclosed and claimed.

Reduce power by frame skipping

Embodiments described herein provide an apparatus comprising a plurality of processing resources including a first processing resource and a second processing resource, a memory communicatively coupled to the first processing resource and the second processing resource, and a processor to receive data dependencies for one or more tasks comprising one or more producer tasks executing on the first processing resource and one or more consumer tasks executing on the second processing resource and move a data output from one or more producer tasks executing on the first processing resource to a cache memory communicatively coupled to the second processing resource. Other embodiments may be described and claimed.

Data locality enhancement for graphics processing units

Apparatuses including a graphics processing unit, graphics multiprocessor, or graphics processor having an error detection correction logic for cache memory or shared memory are disclosed. In one embodiment, a graphics multiprocessor includes cache or local memory for storing data and error detection correction circuitry integrated with or coupled to the cache or local memory. The error detection correction circuitry is configured to perform a tag read for data of the cache or local memory to check error detection correction information.

Systems and methods for error detection and control for embedded memory and compute elements

An apparatus includes at least one memory, instructions, and processor circuitry to execute the instructions to track movement of a head of a user wearing earphones, the earphones to move with the movement of the head of the user, the earphones to be communicatively coupled to a computing device. The processor circuitry is to obtain media content, the media content including first audio data for a first channel and second audio data for a second channel. The processor circuitry is to adjust, based on the movement of the head of the user, the first audio data for the first channel and the second audio data for the second channel. The processor circuitry is to cause the adjusted first audio data and the adjusted second audio data to be played by the earphones.

Audio spatialization

Methods and apparatus relating to techniques for avoiding cache lookup for cold cache. In an example, an apparatus comprises logic, at least partially comprising hardware logic, to collect user information for a user of a data processing device, generate a user profile for the user of the data processing device from the user information, and set a power profile a processor in the data processing device using the user profile. Other embodiments are also disclosed and claimed.

Processor power management

Systems, apparatuses and methods may provide away to render augmented reality (AR) and/or virtual reality (VR) sensory enhancements using ray tracing. More particularly, systems, apparatuses and methods may provide a way to normalize environment information captured by multiple capture devices, and calculate, for an observer, the sound sources or sensed events vector paths. The systems, apparatuses and methods may detect and/or manage one or more capture devices and assign one or more the capture devices based on one or more conditions to provide observer an immersive VR/AR experience.

Augmented reality virtual reality ray tracing sensory enhancement system, apparatus and method

In accordance with some embodiments, the render rate is varied across and/or up and down the display screen. This may be done based on where the user is looking in order to reduce power consumption and/or increase performance. Specifically the screen display is separated into regions, such as quadrants. Each of these regions is rendered at a rate determined by at least one of what the user is currently looking at, what the user has looked at in the past and/or what it is predicted that the user will look at next. Areas of less focus may be rendered at a lower rate, reducing power consumption in some embodiments.

Regional adjustment of render rate

An embodiment of an electronic processing system may include an application processor, persistent storage media communicatively coupled to the application processor, a graphics subsystem communicatively coupled to the application processor, an object space adjuster communicatively coupled to the graphics subsystem to adjust an object space parameter based on a screen space parameter, and a sample adjuster communicatively coupled to the graphics subsystem to adjust a sample parameter of the graphics subsystem based on a detected condition. Other embodiments are disclosed and claimed.

Graphics with adaptive temporal adjustments

In an example, an apparatus comprises logic, at least partially comprising hardware logic, to power on a first set of processing clusters, dispatch a workload to the first set of processing clusters, detect a full operating state of the first set of processing clusters, and in response to the detection of a full operating state of the first set of processing clusters, to power on a second set of processing clusters. Other embodiments are also disclosed and claimed.

Dynamically power on/off processing clusters during execution

Dynamic power budget allocation in a multi-processor system is described. In an example, an apparatus includes a plurality of processor units; and a power control component, the power control component to monitor power utilization of each of the plurality of processor units, wherein power consumed by the plurality of processor units is limited by a global power budget. The apparatus is to assign a workload to each of the processor units and is to establish an initial power budget for operation of each of the processor units, and, upon the apparatus determining that one or more processor units require an increased power budget based on one or more criteria, the apparatus is to dynamically reallocate an amount of the global power budget to the one or more processor units.

Dynamic power budget allocation in multi-processor system

Systems, apparatuses and methods may provide for technology that determines a frame rate of video content, sets a blend amount parameter based on the frame rate, and temporally anti-aliases the video content based on the blend amount parameter. Additionally, the technology may detect a coarse pixel (CP) shading condition with respect to one or more frames in the video content and select, in response to the CP shading condition, a per frame jitter pattern that jitters across pixels, wherein the video content is temporally anti-aliased based on the per frame jitter pattern. The CP shading condition may also cause the technology to apply a gradient to a plurality of color planes on a per color plane basis and discard pixel level samples associated with a CP if all mip data corresponding to the CP is transparent or shadowed out.

Synergistic temporal anti-aliasing and coarse pixel shading technology

Embodiments described herein are generally directed to improvements relating to power, latency, bandwidth and/or performance issues relating to GPU processing/caching. According to one embodiment, a system includes a producer intellectual property (IP) (e.g., a media IP), a compute core (e.g., a GPU or an AI-specific core of the GPU), a streaming buffer logically interposed between the producer IP and the compute core. The producer IP is operable to consume data from memory and output results to the streaming buffer. The compute core is operable to perform AI inference processing based on data consumed from the streaming buffer and output AI inference processing results to the memory.

Graphics processing unit processing and caching improvements

Growing community of inventors

Lincoln, CA, United States of America

Nikos Kaburlasos