Intel Corporation

Nikolay Kosarev

Sergey Y Shishlov

Alexander V Butuzov

Jayesh Iyer

Boris A Babayan

Alexey Sivtsov

Vladimir M Pentkovski

Andrey Kluchnikov

Vladimir Penkovski

Yuriy V Baida

Bob Babayan

Sergey V Bulenkov

A processor includes a first logic to execute an instruction stream out-of-order, the instruction stream divided into a plurality of strands, the instruction stream and each strand ordered by program order (PO). The processor also includes a second logic to determine an oldest undispatched instruction in the instruction stream and store an associated PO value of the oldest undispatched instruction as an executed instruction pointer. The instruction stream includes dispatched and undispatched instructions. The processor also includes a third logic to determine a most recently retired instruction in the instruction stream and store an associated PO value of the most recently retired instruction as a retirement pointer, a fourth logic to select a range of instructions between the retirement pointer and the executed instruction pointer, and a fifth logic to identify the range of instructions as eligible for retirement.

Instruction and logic for identifying instructions for retirement in a multi-strand out-of-order processor

A computer system, a processor in a computer and a computer-implemented method executable on a computer processor involve dividing a set of computer instructions arranged in a sequential program order into a plurality of instruction sequences. Instructions within each sequence are arranged according to the program order. An increment value is assigned to a preceding instruction in each sequence. The increment value is equal to a difference between a program order value of a subsequent instruction in the sequence and a program order value of the preceding instruction. The processor calculates the program order value of each subsequent instruction based on the program order value and the increment value of a corresponding preceding instruction in the same sequence.

Method and apparatus for reconstructing real program order of instructions in multi-strand out-of-order processor

A computer system, a computer processor and a method executable on a computer processor involve placing each sequence of a plurality of sequences of computer instructions being scheduled for execution in the processor into a separate queue. The head instruction from each queue is stored into a first storage unit prior to determining whether the head instruction is ready for scheduling. For each instruction in the first storage unit that is determined to be ready, the instruction is moved from the first storage unit to a second storage unit. During a first processor cycle, each instruction in the first storage unit that is determined to be not ready is retained in the first storage unit, and the determining of whether the instruction is ready is repeated during the next processor cycle. Scheduling logic performs scheduling of instructions contained in the second storage unit.

Method and apparatus for reducing area and complexity of instruction wakeup logic in a multi-strand out-of-order processor

A processing device comprises select logic to schedule a plurality of instructions for execution. The select logic calculates a reconstructed program order (RPO) value for each of a plurality of instructions that are ready to be scheduled for execution. The select logic creates an ordered list of instructions based on the delayed RPO values, the delayed RPO values comprising the calculated RPO values from a previous execution cycle, and dispatches instructions for scheduling based on the ordered list.

Select logic for the instruction scheduler of a multi strand out-of-order processor based on delayed reconstructed program order

In accordance with embodiments disclosed herein, there are provided methods, systems, and apparatuses for scheduling instructions in a multi-strand out-of-order processor. For example, an apparatus for scheduling instructions in a multi-strand out-of-order processor includes an out-of-order instruction fetch unit to retrieve a plurality of interdependent instructions for execution from a multi-strand representation of a sequential program listing; an instruction scheduling unit to schedule the execution of the plurality of interdependent instructions based at least in part on operand synchronization bits encoded within each of the plurality of interdependent instructions; and a plurality of execution units to execute at least a subset of the plurality of interdependent instructions in parallel.

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Yoshkar-Ola, Russia

Nikolay Kosarev