Texas Instruments Corporation

Ericsson Gmbh

Telefonaktiebolaget Lm Ericsson (publ)

Qorvo Us, Inc.

Samsung Electronics Co., Ltd.

St-ericsson Sa

Analog Devices,inc.

Oct Circuit Technologies International Limited

Nikolaus Klemmer

Hunsoo Choo

Timothy Patrick Pauletti

Abhijit Anant Patki

Amneh Mohammed Akour

Paul Wilkinson Dent

Tarkesh Pande

Charles Kasimer Sestok, Iv

Venkatesh Srinivasan

Kelly M Lear

Hamid Safiri

Xiaoxi Bruce Zhang

Kun Shi

Victoria Wang

David K Homol

Magnus Nilsson

Rahmi Hezar

Siraj Akhtar

Frederick L Martin

Gangadhar Burra

Jaimin A Mehta

Srinadh Madhavapeddi

Himanshu Arora

Jeffery D Galipeau

Steven L White

Fikret Dulger

Amneh Mohammad Akour

Satish V Uppathil

Ali S Khayrallah

Chris Levesque

Paul Edward Gorday

Antonio J Montalvo

Wael Al-Qaq

Joel L Dawson

Tracy Lawrence Fulghum

Zhihang Zhang

Petteri Matti Litmanen

Bror Peterson

Alan R Holden

John Stewart Petty, Jr

Domenico Arpaia

Jaiminkumar Mehta

Wenjing Lu

Lu Sun

Vijayavardhan Baireddy

Theron Jones

Atul Kumar Jain

Steven White

Jeffrey Gengler

Al Jacoutot

Satish Uppathil

Chan Fernando

Rached Hajjii

Amin Shahverdi

Elias Reese

Mark Briffa

Embodiments of an acoustic filter are disclosed. In some embodiments, a bandpass filter is included in a passband signal path, the passband signal path is connected between a first terminal and a second terminal. A first bandstop filter is located in a first stopband signal path, the first stopband signal path connected at the first terminal. Additionally, a second bandstop filter is located in a second stopband signal path, the second stopband signal path is connected at the second terminal.

Acoustic filters with improved return loss

A reactance cancelling radio frequency (RF) circuit array is disclosed. The reactance cancelling RF circuit array includes multiple RF circuits each coupled to one or two adjacent RF circuits by one or two pairs of coupling mediums each having a respective length less than one-quarter wavelength. In one aspect, an RF input signal is first split across the RF circuits and then combined to form an RF output signal. As a result, each RF circuit requires a lower power handling capability to process a portion of the RF input signal. In another aspect, each pair of the coupling mediums can cause reactance cancellation in each reactance-cancelling pair of the RF circuits. By coupling the RF circuits via the coupling mediums and enabling splitting-combining among the RF circuits, it is possible to miniaturize the reactance cancelling RF circuit array for improved performance across a wide frequency spectrum.

Reactance cancelling radio frequency circuit array

A power amplifier with a quasi-static drain voltage adjustment is provided that has a transistor that is made from Gallium Nitride (GaN). In an exemplary aspect, the transistor is a field-effect transistor (FET) having a source, gate, and drain. The transistor is tested for process variations. Based on detected process variations, a microcontroller may raise a drain voltage to increase output power capability. Power capability of the power amplifier scales as the square of the drain voltage, so small adjustments are sufficient to offset the slow process corner while maintaining reliability.

Power amplifier with quasi-static drain voltage adjustment

A digital compensation system for a radio frequency (RF) power amplifier module is disclosed. The digital compensation system includes an RF power amplifier having a first input, a first output, and a first bias input, wherein the RF power amplifier is configured to receive an RF signal at the first input and generate an amplified version of the RF signal at the first output. The digital compensation system also includes compensation circuitry coupled between the first input and the first output and a bias output coupled to the RF power amplifier, wherein the compensation circuitry is configured, in response to the RF signal, to generate or adjust a bias signal at the first bias input to correct dynamic bias errors caused by amplification variations that have time constants.

Digital compensation system for a radio frequency power amplifier module

A transceiver for low-complexity beam steering. The transceiver has a first antenna array including a first sub-aperture with a first native beam steering angle and a second antenna array including a second sub-aperture with a second native beam steering angle different than the first native beam steering angle. The first antenna array and the second antenna array are arranged in the transceiver such that the first sub-aperture is combinable with the second sub-aperture to form a combined aperture when the first antenna array and the second antenna array are excited.

Low-complexity beam steering in array apertures

A power-on-reset (POR) circuit for CMOS logic is operable to transition between a POR_active state and a POR_inactive state and can include: (a) VDD/VT threshold circuitry to provide a Vtp_threshold voltage based on input Vdd and PMOS Vtp, and a Vtn_threshold voltage based on input Vdd and NMOS Vtn; (b) POR transition detect circuitry to provide a POR_transition signal (active/inactive) based on a function (Vtp, Vtn), which is a function of Vtp_threshold and Vtn_threshold; and (c) POR transition control circuitry to provide the POR_state signal (active/inactive) based on the POR_transition signal. For a POR out-of-reset transition, the POR transition detect circuitry to switch the POR_transition signal inactive based on the function (Vtp, Vtn) corresponding to the POR_inactive state, and the POR transition control circuitry, responsive to the POR_transition signal switching to inactive, to initiate a POR out-of-reset delay period, and to signal the POR_inactive state after the POR out-of-reset delay period.

Power-on reset circuit with reset transition delay

An integrated circuit includes a bit slicing circuit with a processing circuit. The processing circuit receives discrete frequency power estimates based on an S-FSK waveform received by an S-FSK receiver associated with the bit slicing circuit. The discrete frequency power estimates are representative of digital logic levels in a series of data frames modulated using S-FSK to form the S-FSK waveform. Each data frame including at least one word. Each word includes bit periods. The processing circuit receives SNR parameters that represent a dynamic SNR for the respective discrete frequency power estimates in relation to the series of data frames. The processing circuit selects a bit slicing technique from a set of available bit slicing techniques to generate data bit values for bit periods of the discrete frequency power estimates based on the SNR parameters. A method for performing bit slicing in an S-FSK receiver is also disclosed.

Bit slicer circuit for S-FSK receiver, integrated circuit, and method associated therewith

A mobile electronic device includes a plurality of radio frequency (RF) antennas and a processor. RF antennas are configured to transmit (TX) or receive (RX) a RF signal. The processor is configured to configure one RF antenna, among the plurality of RF antenna, as a TX antenna and remaining RF antennas as RX antennas, cause the TX antenna to transmit the RF signal, cause the RX antennas to receive portions of the RF signal, the portions reflected from an object, calculate each of flight times of the RF signal with respect to each of the RX antennas, and identify a location of the object based on each of flight times of the RF signal, wherein each of the plurality of RF antennas is reconfigurable as the TX antenna or the RX antennas. A method for operating a mobile device is also provided.

Detection and ranging using multi-radio mobile devices

A front-end receiver includes a first mixer of a first channel, a second mixer of a second channel, and a switching circuit that is configured to select the first mixer or the second mixer during a particular time period. Upon being selected, one of the first mixer or the second mixer is configured to deliver a down-converted signal that down-converts a respective RF signal of either the first or second reception channel. As the tasks of down-conversion and multiplexing are combined at the mixer level, the first and second reception channels may share a baseband circuit while being able to provide a well-balanced metrics of channel isolation, low noise figure, and linearity.

Front-end transceivers with multiple reception channels

A threshold computation circuit includes an input circuit, a maximum filter circuit, a minimum filter circuit, and a calculating circuit. The input circuit receives a discrete frequency signal from a digital filtering circuit. The discrete frequency signal is based on an S-FSK waveform received by an S-FSK receiver associated with the digital filtering circuit. The discrete frequency signal is representative of digital logic levels in a series of data frames modulated using S-FSK to form the S-FSK waveform. The maximum filter circuit adjusts a maximum amplitude parameter based on the discrete frequency signal and a predetermined threshold. The minimum filter circuit adjusts a minimum amplitude parameter based on the discrete frequency signal and the predetermined threshold. The calculating circuit adapts the predetermined threshold for a next data frame based on the maximum and minimum amplitude parameters. An integrated circuit and a method for computing the threshold are also disclosed.

Threshold computation circuit for S-FSK receiver, integrated circuit, and method associated therewith

System and methods for input path matching in pipelined continuous-time Analog-to Digital Converters (ADCs), including pipelined Continuous-Time Delta Sigma Modulator (CTDSM) based ADCs, includes an input delay circuit disposed in a continuous-time input path from an input of an analog input signal to a first summing circuit of the continuous-time ADC. At least one digital delay line is disposed between an output of an earlier stage sub-ADC (of a plurality of pipelined sub-ADCs) and a sub-digital-to-analog converter (DAC) that is coupled to the first summing circuit, and between the earlier stage sub-ADC and a digital noise cancellation filter. The digital delay line(s) is configured to enable calibration of delay of output of the earlier stage sub-ADC provided to the sub-DAC and the digital noise cancellation filter in accordance with process variations of the input delay match circuit to minimize residue output at first summing circuit.

Input path matching in pipelined continuous-time analog-to-digital converters

A power-on-reset (POR) circuit for CMOS logic is operable to transition between a POR_active state and a POR_inactive state and can include: (a) VDD/VT threshold circuitry to provide a Vtp_threshold voltage based on input Vdd and PMOS Vtp, and a Vtn_threshold voltage based on input Vdd and NMOS Vtn; (b) POR transition detect circuitry to provide a POR_transition signal (active/inactive) based on a function(Vtp,Vtn), which is a function of Vtp_threshold and Vtn_threshold; and (c) POR transition control circuitry to provide the POR_state signal (active/inactive) based on the POR_transition signal. For a POR out-of-reset transition, the POR transition detect circuitry to switch the POR_transition signal inactive based on the function (Vtp,Vtn) corresponding to the POR_inactive state, and the POR transition control circuitry, responsive to the POR_transition signal switching to inactive, to initiate a POR out-of-reset delay period, and to signal the POR_inactive state after the POR out-of-reset delay period.

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Dallas, TX, United States of America

Nikolaus Klemmer