International Business Machines Corporation

Globalfoundries Inc.

Hgst Netherlands, B.v.

Other

Nikolaos Papandreou

Charalampos Pozidis

Roman Alexander Pletka

Nikolas Ioannou

Timothy J Fisher

Sasa Tomic

Aaron Daniel Fry

Thomas Mittelholzer

Thomas P Parnell

Radu Ioan Stoica

Charles John Camp

Abu Sebastian

Milos Stanisavljevic

Andrew Dale Walls

Angeliki Pantazi

Tobias Blaettler

Evangelos Stavros Eleftheriou

Ioannis Koltsidas

Andreea Anghel

Haris Pozidis

Gary A Tressler

Adalberto Guillermo Yanes

Kevin E Sallese

Tomas Tuma

Jason Szecheong Ma

Theodore Antonakopoulos

Van Huynh

Charles A Keller

Urs Frey

Daniel Frank Moertl

Robert Edward Galbraith

Jan Van Lunteren

Damir Anthony Jamsek

Andrew Kenneth Martin

Thomas J Griffin

M Dean Sciacca

Mussie T Negussie

Dimitrios Sarigiannis

Jenny L Brown

Celestine Mendler-Duenner

Sonali Andani

Abu Sabastian

Matt Reuter

According to one embodiment, a method, computer system, and computer program product for training a cognitive model that involves one or more decision trees as base learners is provided. The present invention may include constructing, by a tree building algorithm, the one or more decision trees, wherein the constructing further comprises associating one or more training examples with one or more leaf nodes of the one or more decision trees and iteratively running a breadth-first search tree builder on one or more of the decision trees to perform one or more tree building operations; and training the cognitive model based on the one or more decision trees.

Training decision tree-based predictive models

A non-volatile memory includes physical blocks each including a respective plurality of cells, where each cell is capable of storing multiple bits of data. A controller maintains dynamically resizable pools of physical blocks, including at least a low-density pool in which cells are configured to store fewer bits and a high-density pool in which cells are configured to store more bits. The controller repeatedly dynamically resizes the low-density and the high-density pools based on write utilization of the non-volatile memory.

Storage pool resizing to meet memory endurance targets

The invention relates to a method of operating a memory device comprising memory cells for storing information on N voltage levels separated by N−1 threshold voltages, the method comprising: obtaining a plurality of threshold voltage shift (TVS) patterns, each comprising N−1 TVS reference values representing expected shifts of the threshold voltages of a set of memory cells having a specific physical condition; assigning a matching TVS pattern to the set of memory cells; storing differences between actual TVS values of the memory cells and corresponding TVS reference values of the matching TVS pattern as TVS residual values; upon a reading instruction for a specified memory cell, determining restored TVS values by combining the matching TVS pattern of the corresponding set of memory cells with corresponding TVS residual values; and reading the information from the specified cell using the restored TVS values.

Storage of threshold voltage shifts

A technique for writing data to pages in a QLC block of a QLC NAND flash memory device, where the device comprises a plurality of SLC pages organized in SLC blocks and a plurality of QLC pages organized in QLC blocks. The technique comprises storing received data in SLC pages, dividing equally a QLC block in a predefined number of sub-blocks according to a corresponding QLC page health status of the pages of the QLC block. Upon determining that SLC pages are to be copied from SLC pages to QLC pages, copying device-internal the respective SLC pages to the sub-blocks of the QLC block using device-internal cache registers, where the copying is based on an error-count aware scheme.

Write and retire pages in QLC NAND blocks

An approach of accelerating inferences based on decision trees based on accessing one or more decision trees, wherein each decision tree of the decision trees accessed comprises decision tree nodes, including nodes grouped into one or more supersets of nodes designed for joint execution. For each decision tree of the decision trees accessed, the nodes are executed to obtain an outcome for the one or more decision trees, respectively. For each superset of the one or more supersets of said each decision tree, the nodes of each superset are jointly executed by: loading attributes of the nodes of each superset in a respective cache line of the cache memory processing said attributes from the respective cache line until an inference result is returned based on the one or more outcomes.

Joint execution of decision tree nodes for accelerating inferences

A non-volatile memory includes physical blocks each including a respective plurality of cells, where each cell is capable of storing multiple bits of data. A controller maintains dynamically resizable pools of physical blocks, including at least a low-density pool in which cells are configured to store fewer bits and a high-density pool in which cells are configured to store more bits. The controller determines whe ther total utilization of physical blocks is less than a low-density pool utilization threshold above which the high-density pool of physical blocks is utilized for storing host write data and additionally identifies cold in-use logical block address (LBA) regions having low total access frequencies. Based on determining the total utilization of physical blocks is less than the low-density pool utilization threshold, the controller performs data placement of data from the cold in-use LBA regions in blocks of the high-density pool.

Proactive data placement in high density storage by a hybrid non-volatile storage controller

Threshold voltage shift values, or TVS values, are calibrated for a non-volatile memory unit including strings of memory cells organized into memory pages, the memory pages being organized into blocks. The calibration involves a read operation to read a given page of the memory pages, based on given one or more TVS values for the given page. In response to a read failure of the read operation, the calibration determines one or more corrected TVS values based on one or more reference TVS values of one or more reference pages of the memory pages. The calibration subsequently performs a read operation to read the given page based on the one or more corrected TVS values. This calibration exploits TVS values of reference pages to determine corrected TVS values of the failing page, instead of finding appropriate TVS values by repeatedly re-reading the failing page.

Calibration of threshold voltage shift values

A method for intra-block recovery from memory page read failures of memory pages is provided. The method comprises providing a data storage device comprising a plurality of memory pages. Corresponding memory pages are physically organized as a plurality of blocks comprising each the corresponding pages, each memory page comprising a plurality of non-volatile memory cells. The method comprises grouping memory pages of a block into at least one window. Each window comprises a plurality of memory pages of the block. The method further comprises determining a window parity page for each window of the block for a recovery of page read failures of the memory pages of the block, and upon determining that a predefined number of memory pages of the window is written or not yet written, maintaining the determined window parity page as part of the related window of memory pages of the block or not.

Addressing page-correlated read issues using intra-block parity

A non-volatile memory includes a plurality of cells each individually capable of storing multiple bits of data including bits of multiple physical pages. A controller of the non-volatile memory issues a command to perform a programming pass for a physical page among the multiple physical pages. The controller determines whether or not the programming pass took less than a minimum threshold time and no program fail status indication was received. Based on determining the programming pass took less than a minimum threshold time and no program fail status indication was received, the controller detects an under-programming error and performs mitigation for the detected under-programming error.

Detecting and managing under-program failures in non-volatile memory

A controller of a non-volatile memory detects errors in data read from a particular physical page of the non-volatile memory. Based on detecting the errors, the controller performs a read voltage threshold calibration for a page group including the particular physical page and a multiple other physical pages. Performing the read voltage threshold calibration includes calibrating read voltage thresholds based on only the particular physical page of the page group. After the controller performs the read voltage threshold calibration, the controller optionally validates the calibration. Validating the calibration includes determining whether bit error rates diverge within the page group and, if so, mitigating the divergence. Mitigating the divergence includes relocating data from the page group to another block of the non-volatile memory.

Page group read voltage threshold calibration

A method, system, and computer program product are disclosed. The method includes receiving a write request to a system and calculating, based on operating parameters of the system, a total processing time associated with servicing the write request in the system. The method also includes determining an actual time taken to store data specified in the write request and, when the actual time is less than the total processing time, delaying sending a completion message for the write request to an I/O interface.

Latency in data storage systems

In an approach for constructing an ensemble model from a set of base learners, a processor performs a plurality of boosting iterations, where: at each boosting iteration of the plurality of boosting iterations, a base learner is selected at random from a set of base learners, according to a sampling probability distribution of the set of base learners, and trained according to a training dataset; and the sampling probability distribution is altered: (i) after selecting a first base learner at a first boosting iteration of the plurality of boosting iterations and (ii) prior to selecting a second base learner at a final boosting iteration of the plurality of boosting iterations. A processor constructs an ensemble model based on base learners selected and trained during the plurality of boosting iterations.

Constructing an ensemble model from randomly selected base learners

A non-volatile memory includes a plurality of physical blocks each including a respective plurality of cells, where each cell is individually capable of storing multiple bits of data. A controller for the non-volatile memory maintains dynamically resizable pools of physical blocks, including at least a low-density pool of physical blocks in which cells are configured to store a fewer number of bits and a high-density pool of physical blocks in which cells are configured to store a greater number of bits. The controller detects an imbalance in utilization between the low-density and high-density pools and, based on detection of the pool imbalance, restricts data placement in the low-density pool, enables garbage collection from the low-density pool back into the low-density pool to compact the low-density pool, and re-enables data placement to the low-density pool based on availability of a threshold number of free physical blocks in the low-density pool.

Balancing utilization of memory pools of physical blocks of differing storage densities

A computer-implemented method, according to one embodiment, includes: maintaining a first subset of the plurality of blocks in a first pool, where the blocks maintained in the first pool are configured in SLC mode. A second subset of the plurality of blocks is maintained in a second pool, where the blocks maintained in the second pool are configured in multi-bit-per-cell mode. A current I/O rate for the memory is identified during runtime, and a determination is made as to whether the current I/O rate is outside a first range. In response to determining that the current I/O rate is not outside the first range, the blocks maintained in the first pool are used to satisfy incoming host writes. Moreover, in response to determining that the current I/O rate is outside the first range, the blocks maintained in the second pool are used to satisfy incoming host writes.

Workload based relief valve activation for hybrid controller architectures

A memory controller receives a multi-plane read request and identifies a set of actual read offsets for a set of pages in the multi-plane read request. The memory controller calculates a common read offset using the set of actual read offsets. The memory controller calculates an offset difference for. Each page. Each offset difference reflects the difference between an actual read offset for that page and the common read offset. The memory controller compares a particular page's offset difference to an offset difference threshold. The memory controller categorizes, based on the comparing, a first subset of pages from the set of pages into a single plane group and a second subset of pages from the set of pages into a multi-plane group. The memory controller performs a multi-plane read on the multi-plane group.

Triage of multi-plane read requests

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Thalwil, Switzerland

Nikolaos Papandreou