Avago Technologies General IP (Singapore) Pte. Ltd.

Nikola Radovanovic

Krishnan Srinivasan

Igor V Kucherenko

An apparatus having a first memory circuit, a plurality of arithmetic modules, and a plurality of second memory circuits. The first memory circuit may be configured to read or write data to or from a host. The plurality of arithmetic modules each may be configured to be enabled or disabled in response to control signals received from the first memory circuit. The plurality of second memory circuits may be configured to read or write data to or from the first memory circuit through a data exchange layer. The arithmetic modules provide cryptographic protection of the data.

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San Jose, CA, United States of America

Nikola Radovanovic