Fujitsu Corporation

Nvidia Corporation

Nikola Nedovic

William Warren Walker

Sudhir Shrikantha Kudva

Shuo-Chun Kao

Sanquan Song

Stephen G Tell

Carl Thomas Gray

Scott McLeod

Nestor Tzartzanis

Brian Matthew Zimmer

Xuan Tan

H Anders Kristensson

John Wood Poulton

Hirotaka Tamura

Xi Chen

Tony Shuo-Chun Kao

Vojin G Oklobd{haeck Over (z)}ija

John M Wilson

Samir Parikh

Walker Joseph Turner

Pradip Thachile

Mahmut Ersin Sinangil

Ahmed Abou-Alfotouh

Yan He

Vojin G Oklobdzija

Volin G Oklobdzija

A glitch detection device includes an oscillator to generate multiple local clocks of multiple different phases and a sampling circuit to oversample, using the multiple local clocks, a system clock to generate multiple samples of the system clock. The device further includes a glitch detector to monitor a variation in pulse width of the system clock based on counting the multiple samples and to report a glitch in response to detecting a variation in the pulse width that exceeds a threshold value.

Frequency-locked and phase-locked loop-based clock glitch detection for security

PUF cells utilizing a dual-interlocking scheme demonstrating improved noise immunity and stability across different V/T conditions and different uses over time in noisy environments. The PUF cell may be advantageously utilized in conjunction with error detection techniques that screen out unstable cells. A set of such PUF cells utilized to generate a device-specific bit pattern, for example a master key.

Physically unclonable cell using dual-interlocking and error correction techniques

A glitch detection device includes an oscillator to generate multiple local clocks of multiple different phases and a sampling circuit to oversample, using the multiple local clocks, a system clock to generate multiple samples of the system clock. The device further includes digital logic that in turn includes a glitch detector to monitor a variation in pulse width of the system clock based on counting the multiple samples and to report a glitch in response to detecting a variation in the pulse width that exceeds a threshold value. The digital logic further includes a loop filter coupled between the glitch detector and the oscillator. The loop filter variably adjusts the oscillator based on a frequency of each of the multiple samples to control an output frequency of each of the multiple different phases of the oscillator.

A circuit includes a set of multiple bit generating cells. One or more adjustable characterization circuits are coupled to inputs to the bit generating cells to affect the outputs of the bit generating cells. Based on the effect of the characterization circuit(s) on the outputs of the bit generating cells, a subset less than all of the bit generating cells is selected.

Detection and mitigation of unstable cells in unclonable cell array

Bit generating cells are subjected to processes that accelerate aging-related characteristics before they are configured for use in the field (enrolled). Aging improves the reliability of the cells by shifting device characteristic in a direction that improves the cell behavior with respect not only to aging but also environment variations. Outputs of the cells are read, and the cells are reconfigured with a bias to output an opposite value, and then aged for enrollment.

Stability of bit generating cells through aging

Various implementations of a current flattening circuit are disclosed, including those utilizing a feedback current regulator, a feedforward current regulator, and a constant current source.

Current flattening circuit for protection against power side channel attacks

This disclosure relates to current flattening circuits for an electrical load. The current flattening circuits incorporate randomize various parameters to add noise onto the supply current. This added noise may act to reduce the signal to noise ratio in the supply current, increasing the difficulty of identifying a computational artifact signal from power rail noise.

Techniques to improve current regulator capability to protect the secured circuit from power side channel attack

A circuit includes a set of multiple bit generating cells. One or more adjustable current sources is coupled to introduce perturbations into outputs of the bit generating cells. Based on the perturbations, the outputs of a subset less than all of the bit generating cells are selected, and applied as a control.

A receiver circuit includes a clock lane propagating a clock signal. A self-sampled clock applies a delayed version of the clock signal to the clock signal and compensation logic controls an amount of delay of the delayed version of the clock, based on a reference voltage offset (difference) between the receiver and a transmitter. The delayed version of the clock is centered on one unit interval of the clock. An offset correction based on a clock duty cycle error is applied to data receiver front ends.

Reference noise compensation for single-ended signaling

A receiver circuit includes a clock lane propagating a clock signal. A self-sampled clock applies a delayed version of the clock signal to the clock signal and compensation logic controls an amount of delay of the delayed version of the clock, based on a reference voltage offset (difference) between the receiver and a transmitter. The delayed version of the clock is centered on one unit interval of the clock. An offset correction is computed as a global offset value based on a clock duty cycle error, combined with a local offset value for each data lane, and is applied to data receiver front ends.

A linear regulator for applications with low area constraint resulting in limited load decoupling capacitance that introduces a compensating zero in the regulator loop to counteract the loss of phase margin and further introduces a feed-forward noise cancellation path operating over a wide frequency range covering a first package resonance frequency. The feed-forward path has low power consumption and improves the power-supply rejection ratio.

Low area voltage regulator with feedforward noise cancellation of package resonance

According to some embodiments, the present disclosure may relate to a method of neural network analysis that includes receiving a first electronic message, storing it in a storage device, and decoding it to output a first data structure. The first electronic message may reference a first dictionary entry correlating the first electronic message to the first data structure including more bits than the first message. The method may also include providing the first data structure to a processing element to perform a data structure analysis on the first data structure yielding a second data structure including more bits than the first electronic message. The method may also include matching the second data structure to a second dictionary entry correlating the second data structure to a second electronic message that includes fewer bits than the second data structure, and transmitting the second electronic message instead of the second data structure.

Neural network analysis

A DC-DC converter circuit includes a switched tank converter configured to output a switching waveform. The DC-DC converter circuit further includes a transformer coupled to the switched tank converter to receive the switching waveform output by the switched tank converter across a primary winding of the transformer.

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San Jose, CA, United States of America

Nikola Nedovic