Apple Inc.

Nikola Jovanovic

Michael Couleur

Nicola Rasera

Siarhei Meliukh

Shawn Searles

Jay B Fletcher

Sanjay Pant

Talbott Mead Houk

Fabio Ongaro

Nathan F Hanagami

Di Zhao

Wenxun Huang

Frank Trautmann

Floyd L Dankert

Alessandro Molari

Andrea Acquas

Hartmut Sturm

Ludmil N Nikolov

Tristan R Hudson

Bhanupriya Suresh

Seyedeh Maryam Mortazavi Zanjani

Nicola Florio

Chad L Olson

Pietro Gabriele Gambetta

John J Sullivan

Jonathan A Dutra

The present disclosure describes a system with a power management device, a wakeup circuit, a battery management device, and a connector. During a powered down mode of operation, the battery management device can provide, via the connector, a bias voltage to the wakeup circuit. In response to a wakeup switch being activated, the battery management device can provide a power supply (e.g., from a battery) to the power management device. Benefits of the wakeup circuit include (1) a reduction of battery consumption—and thus improving battery lifetime—when the electronic system is in a powered down mode of operation because the wakeup circuit has lower number of active components compared to other designs and (2) a non-complex wakeup circuit design because one or more existing connector interconnects between the power management device and the battery management device can be re-used during electronic system's powered down mode of operation.

Wakeup circuit

A multi-level power converter circuit for computer systems maintains phase alignment with other power converter circuits by employing low-gain phase-locked loop circuits. In order to account for different voltage levels on its terminal nodes, the power converter circuit may perform a comparison of the respective voltage levels of its terminal nodes. Using results of the comparison, the power converter circuit can select different regulation modes using different ones of the low-gain phase-locked loop circuits.

Multi-level power converter with low-gain phase-locked loop control

A power converter circuit included in a computer system may employ a compensation loop to adjust the durations of active times during which the power converter circuit sources energy to a load circuit via an inductor. The compensation loop includes an error signal whose value is based on a difference in the output voltage of the power converter circuit from a desired voltage level. During output transients, the error signal is adjusted using an injection current that tracks current flowing through the inductor.

Bias generation for power converter control

A hysteretic current control switching power converter with a clock-controlled switching frequency is disclosed. A power converter includes a switching circuit including a high side switch and a low side switch coupled to one another at a switching node, with an inductor being coupled between the switching node and a regulated supply voltage node. The power converter further includes a control circuit configured to alternately cause activation of the high side switch and the low side switch, wherein the control circuit is configured to activate the low side switch in response to a first voltage reaching peak threshold value, the first voltage corresponding to a current through the inductor. A ramp voltage circuit is configured to, in response to a clock signal, generate a ramp voltage, wherein the peak threshold value is based on the ramp voltage.

Hysteretic current control switching power converter with clock-controlled switching frequency

A power converter is disclosed. The power converter is configured to provide a regulated output voltage. The power converter includes a first control loop configured to generate a first voltage based on a rate of change of the regulated output voltage. A second control loop is configured to generate a second voltage based on an output current provided by the power converter. An amplifier is configured to generate a third voltage based on the first and second voltages. A control circuit is configured to control the regulated output voltage based on the third voltage.

Voltage regulator with dv/dt detection

A method and apparatus for operating a DC-DC converter in an interleaved (or rotating) pulse frequency modulation (PFM) mode is disclosed. A DC-DC converter includes a number of inductor pairs, with each inductor coupled to a corresponding pulse control circuit. During a cycle in which one of the pulse control circuits sources a current pulse through its respectively coupled inductor, a second pulse control circuit coupled to the other inductor of the pair determines if a voltage on its output node (e.g., where it is coupled to its inductor) is less than a threshold voltage. Responsive to determining that the voltage on its output node is less than the threshold, the second pulse control circuit activates a current path through the other inductor of the pair.

Interleaved pulse frequency modulation mode for a multi-phase buck converter using coupled inductors

A power converter circuit included in a computer system may charge and discharge a switch node coupled to a regulated power supply node via an inductor. The power converter circuit may generate a reference clock signal using a system clock signal and a voltage level of the switch node. The reference clock signal may be used to initiate a charge cycle, whose duration may be based on generated ramp signals.

Power converter with phase error correction

A power converter circuit included in a computer system may charge and discharge a switch node coupled to a regulated power supply node via an inductor. During a discharge cycle, the power converter circuit may sense a current being discharge from the regulated power supply node through the inductor into a ground supply node. The power converter circuit may also sense a noise current flowing in the ground supply node, and generate a control current using both the current being discharge and the noise current. Using the control current, the power converter circuit may halt the discharge cycle.

Noise suppression in voltage regulator circuits

An apparatus includes a plurality of pulse control circuits and a control circuit. A given pulse control circuit of the plurality of pulse control circuits may source a current pulse to the output power signal based on a comparison of a particular feedback signal of a plurality of feedback signals and a target voltage signal. The control circuit may offset a voltage level of each feedback signal of a first subset of the plurality of feedback signals. The first subset may exclude a first feedback signal. In response to a determination that a period of time has ended, the control circuit may offset a voltage level of each feedback signal of a second subset of the plurality of feedback signals. The second subset may include the first feedback signal and exclude a second feedback signal.

Multiphase interleaved pulse frequency modulation for a DC-DC converter

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Munich, Germany

Nikola Jovanovic