Nxp USA, Inc.

Nikhil Tiwari

Maik Brett

Sumit Mittal

Christian Tuschen

Vivek Singh

Sidhartha Taneja

Tejbal Prasad

Saurabh Arora

A processing system including a memory, command sequencers, accelerators, and memory banks. The memory stores program code including instruction threads sequentially listed in the program code. The command sequencers include a master command sequencer and multiple slave command sequencers. The master command sequencer executes the program code including distributing the instruction threads for parallel execution among the slave command sequencers. The instruction threads may be provided inline or accessed via inline thread line pointers. Each accelerator is available to each command sequencer in which multiple command sequencers may access multiple accelerators for parallel execution. The memory banks are simultaneously available to multiple accelerators. The master command sequencer may perform implicit synchronization by waiting for completion of simultaneous execution of multiple instruction threads. A command sequencer arbiter may arbitrate among the command sequencers. A memory bank arbiter may arbitrate among the accelerators for accessing the memory banks.

System and method of obtaining multiple factor performance gain in processing system

A memory controller includes a large combinational cloud to serve multi-core-to-multi-bank memory accesses which causes congestion and routing delays at physical design level especially in lower technology nodes thus limiting the frequency of operation. Present invention proposes an architecture to process sequences of access requests from multiple processing cores using alternating processing to generate sequences of granted access requests to one or more memory banks. For each processing core, first and second buffers store access requests. When an access request from one buffer is granted, that buffer is configured to receive a new access request and processing is performed to determine whether to grant an access request stored in the other buffer. The invention can maintain optimal bandwidth while providing desired sequences of the granted access requests and solving physical congestion issues.

Multi-threaded architecture for memory controller data paths

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Palam Colony, India

Nikhil Tiwari