Nxp B.v.

Nxp Usa, Inc.

Nikhil Sharma

Arvind Kaushik

Stephan Matthias Herrmann

Vivek Mohan Sharma

Sharath Subramanya Naidu

Bhagwan Babu Jha

Rajesh Gupta

Chanpreet Singh

Rushank Patel

Maninder Kumar

A system, method, and apparatus are provided for on-the-fly camera image processing configuring a system-on-chip (SoC) configuration register memory with one or more synchronization settings; processing multiple camera image frame sequences having different specified exposures to detect a set of complete frames from the camera image frame sequences which have a first common frame number; identifying a valid combination of different exposures from the image frame sequences having a second common frame number succeeding the first common frame number; and processing the valid combination of different exposures from the first and second camera image frame sequences to generate output data from the ISP pipeline.

Real time stream camera ISP with loosely coupled control loop

An integrated circuit (IC) includes a memory that stores a thread and a processor that generates an instruction request to retrieve one or more instructions of the thread. The IC further includes an error control circuit that receives the instruction request from the processor and retrieves an instruction of the thread from the memory based on the instruction request. Further, the error control circuit determines whether the retrieved instruction is erroneous. Based on the determination that the retrieved instruction is erroneous, the error control circuit provides a substitute instruction to the processor as a response to the instruction request. The substitute instruction is included in an instruction set of the processor. The processor executes the received substitute instruction and suspends an execution of the thread.

System and method for managing memory errors in integrated circuits

A system that performs a bus transaction includes a transaction controller and a protection code processing circuit. The transaction controller identifies a set of parameters corresponding to the bus transaction based on address and received control information, and modifies at least one parameter or splits the bus transaction into sub-transactions depending on the parameter values to map the bus transaction to a memory address space. The protection code processing circuit generates and inserts a protection code into data to be written to the memory, and removes a protection code from data read from the memory. The system facilitates error checking without requiring modification of the channels (e.g., bus width) used to read and/or write data to memory.

System and method for performing bus transactions

Growing community of inventors

Shimla, India

Nikhil Sharma