Taiwan Semiconductor Manufacturing Comp. Ltd.

Nikhil Puri

Hung-Jen Liao

Yen-Huei Chen

Yu-Hao Hsu

Manish Arora

Yen-huei Chen

Teja Masina

Venkateswara Reddy Konudula

Hidehiro Fujiwara

A semiconductor device includes a first memory array, a first bit line, a second memory array, a second bit line, a first conductive line and a first control circuit. The first bit line crosses over and is coupled to the first memory array, and extends along a first direction. The second bit line crosses over the second memory array, and is coupled to the first bit line. The first conductive line crosses over the second memory array and a part of the first memory array, and is configured to operate as a part of a first capacitor. The first control circuit is configured to couple the first conductive line to the second bit line when the first memory array is written.

Semiconductor device

A semiconductor device includes a first memory bank, a second memory bank and a first write driver. The first memory bank is coupled to a plurality of first data lines, and configured to operate according to a first data signal. The second memory bank is configured to operate according to the first data signal. The first write driver is disposed between the first memory bank and the second memory bank, and configured to adjust a voltage level of one of the plurality of first data lines when the first memory bank is written according to the first data signal.

A memory circuit includes first and second memory segments coupled to first and second write lines, and first and second write line circuits coupled to the first and second write lines and configured to receive first and second data signals. The first and second data signals have complementary low and high logical states during a write operation to the first or second memory segment, and each of the first and second data signals has the low logical state during a masked write operation to the first or second memory segment. The first and second write line circuits output, to the first and second write lines, first and second write line signals responsive to the first and second data signals during the write operation and float the first and second data lines during the masked write operation.

Floating data line circuit and method

A write line circuit includes a power supply node configured to carry a power supply voltage level, a reference node configured to carry a reference voltage level, an output node, first and second switching devices coupled in series between the output node and the power supply node, and a third switching device directly coupled to each of the output node and the reference node. The first switching device is configured to selectively couple the output node to the second switching device responsive to a first data signal, the second switching device is configured to selectively couple the first switching device to the power supply node responsive to a second data signal, and the third switching device is configured to selectively couple the output node to the reference node responsive to the first data signal.

A write line circuit includes a power supply node configured to carry a power supply voltage level, a reference node configured to carry a reference voltage level, a first input node configured to receive a first data signal, a second input node configured to receive a second data signal, a third input node configured to receive a control signal, and an output node. The write line circuit is configured to, responsive to the first data signal, the second data signal, and the control signal, either output one of the power supply voltage level or the reference voltage level on the output node, or float the output node.

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Hsinchu, Taiwan

Nikhil Puri