Cavium, Inc.

Marvell Asia Pte., Ltd.

Xpliant, Inc.

Other

Amazon Technologies, Inc.

Nikhil Jayakumar

Daman Ahluwalia

Vivek Trivedi

Vasant K Palisetti

Amir H Motamedi

Avinash Sodani

Weihuang Wang

Chia-Hsin Chen

Srinivas Sripada

Bhagavati R Mula

Ramacharan Sundararaman

Chirinjeev Singh

Weinan Ma

Gerald Schmidt

Srinath Atluri

Premshanth Theivendran

Atul Bhattarai

Sunil Papanchand Khatri

Sheila Vaidya

Timothy Kevin Griffin

Bhagavathi R Mula

A semiconductor package component (such as a die or interposer) can include a body having a top surface and a bottom surface. The component can further include an interface array arranged along the top surface or the bottom surface. The interface array can include a first set of microbumps arranged in a first row. The interface array can further include a second set of microbumps arranged in a second row adjacent the first row. The interface array can also include a probe pad extending into both the first row and the second row.

High-density microbump and probe pad arrangement for semiconductor components

A system includes a first and a second group of cores in a multicore system. Each core of the first/second group is configured to process data. Each core within the first/second group is configured to enter into an idle state in response to being idle for a first/second period of time respectively. Every idle core in the first/second group is configured to transition out of the idle state and into an operational mode in response to receiving a signal having a first/second value respectively and further in response to having a pending operation to process.

Power management and staggering transitioning from idle mode to operational mode

A power throttling engine includes a register configured to receive a power throttling signal. The power throttling engine further includes a decoder configured to generate a vector based on a value of the power throttling signal. The value of the power throttling signal is an amount of power throttling of a device. The power throttling engine further includes a clock gating logic configured to receive the vector and further configured to receive a clocking signal. The clock gating logic is configured to remove clock edges of the clocking signal based on the vector to generate a throttled clocking signal.

System and method to manage power throttling

Systems and methods for inserting flops at the chip-level to produce a signal delay for preventing buffer overflow are disclosed herein. Shells of modules described in an RTL description and their connections are analyzed to determine a signal latency between a sender block and a receiver block. The logical interfaces of the shells are grouped in a structured document with associated rules. Flops are inserted between the sender block and the receiver block to introduce a flop delay to meet physical design timing requirement and prevent a buffer of the receiver block from overflowing due to data that is already in-flight when a flow control signal is sent by the receiver block. The sum of a delay on a data line and a delay on a flow control line measured in clock cycles must be less than a depth of the buffer.

Approach for chip-level flop insertion and verification based on logic interface definition

An information processing system, device and method wherein a base board is configured to couple to both back and midplane systems as well as optical modules for use in a data center rack system. Specifically, a base board adapter is configured to electrically couple to an integrated backplane/midplane electronic interface of the base board and translate the signals to one or more optical interface module connectors such that one or more optical interface modules are able to be coupled to the base board.

Baseboard interconnection device, system and method

System and method of determining flip-flop counts of interconnects of a physical layout during integrated circuit (IC) design. The outputs of each logic block are defined as primary inputs, and the inputs of each logic block are defined as primary outputs. Each interconnect is traversed from a primary input a primary output to identify the flip-flops and determine the flip-flop count. If an interconnect has a greater flip-flop count than an RTL estimated count, measures are taken to reduce the need for flip-flops with the current routing design. If the interconnect has a smaller flip-flop count than an RTL estimated count, additional flip-flops are inserted.

Determination of flip-flop count in physical design

System and method of automatically performing flip-flop insertions for each net in a logic interface by using the RTL-estimated maximum count as a limit. Based on the timing analysis on the physical layout, a flip-flop insertion count needed for each net is derived and candidate locations for insertions are automatically detected. A set of constraints is applied to identify ineligible locations for flip-flop insertions. If more flip-flop insertions than the count limit are needed to satisfy the timing requirements for a net, timing-related variables are iteratively adjusted using the current layout until the timing requirements can be satisfied using the RTL count limit. If all the nets in the interface need fewer flip-flop insertions than the RTL count limit, the information can be fed back to update the RTL count limit. Each net is then parsed and flip-flops are inserted at appropriated locations.

Automated flip-flop insertions in physical design without perturbation of routing

System and method of automatically performing repeater insertions in physical design of an integrated circuit. Repeaters are inserted in interconnects in a staggered fashion and spaced apart to accommodate potential flip-flop insertions. The sufficient spacing between the repeaters in combination with the staggered pattern ensures that flip-flop insertions can be performed at any of the repeater locations without space limitation. When rerouting is needed following a flip-flop insertion on an interconnect, automatic rerouting is performed but restricted to a short and specified region along the interconnect. Thereby, the resulted alteration from the current routing configuration is minimal and deterministic.

Repeater insertions providing reduced routing perturbation caused by flip-flop insertions

Clock stations in a hybrid tree-mesh clock distribution network are placed and routed using placement information embedded in instance names of the macrocells that form the clock-distribution network. The instance name includes (X,Y) coordinate information corresponding to placement of the macrocell in the physical layout of the network design. Base cells in each macrocell are placed in a known deterministic arrangement, such as one on top of another in a layout of the clock distribution network, all at the same (X,Y) offset. Preferably, the base cells are all from a standard-cell library, thereby reducing design cost and debug.

System for and method of placing clock stations using variable drive-strength clock drivers built out of a smaller subset of base cells for hybrid tree-mesh clock distribution networks

An electronic device fabrication tool uses only standard-size cells from a cell library to fabricate a clock distribution network on a semiconductor device, thereby reducing the cost of the fabrication process. Target clock drive strengths are determined to reduce skew along the clock-distribution network, and the standard size cells are combined to produce clock-driving components substantially equal to the target clock drive strengths. The cells are combined using VIA programming, by electrically coupling them by adding or removing vias connecting the cells. In hybrid tree-mesh clock distribution networks, VIA programming ensures that the binary tree portions of the network are not affected by the tuning. Preferably, the clock-driving elements are clock inverters or buffers, though other elements are able to be used to drive clock signals on the clock distribution network.

System for and method of combining CMOS inverters of multiple drive strengths to create tune-able clock inverters of variable drive strengths in hybrid tree-mesh clock distribution networks

Clock networks constructed with variable drive strength clock drivers are prepared for tuning. The clock drivers are built from a smaller set of base standard cells. Locations of the input and output netlists of the macrocells are marked and reserved even through the extraction process. The macrocells are able to be flattened, generating a netlist with the base cells, and recombined during circuit simulation, thereby reducing the number of iterations, making the tuning flow more efficient. The clock network is initially tuned by adding or removing cross-links in the mesh to balance capacitive loads on each driver of the clock mesh.

System for and method of tuning clock networks constructed using variable drive-strength clock inverters with variable drive-strength clock drivers built out of a smaller subset of base cells

According to one aspect of the present disclosure, a circuit includes a semiconductor device including a plurality of logic blocks and a plurality of programmable interconnects. A delay detector generates a delay signal responsive to a measured delay of an output signal, wherein the output signal is from at least one of the plurality of logic blocks. A biasing circuit responsive to the delay signal to adjust subsequent measured delays toward a predetermined value.

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San Jose, CA, United States of America

Nikhil Jayakumar