International Business Machines Corporation

Nikhil Jain

Ruilong Xie

Sagarika Mukesh

Prabudhya Roy Chowdhury

Kisik Choi

Richard C Johnson

Cody John Murray

Alex Richard Hubbard

Devika Sarkar Grant

Vinay Pai

Fee Li Lie

Tao Li

Liqiao Qin

A semiconductor structure is provided that includes a first FET device region including a plurality of first FETs, each first FET of the plurality of first FETs includes a first source/drain region located on each side of a functional gate structure. A second FET device region is stacked above the first FET device region and includes a plurality of second FETs, each second FET of the plurality of second FETs includes a second source/drain region located on each side of a functional gate structure. The structure further includes at least one first front side contact placeholder structure located adjacent to one of the first source/drain regions of at least one the first FETs, and at least one second front side contact placeholder structure located adjacent to at least one of the second source/drain regions of at one of the second FETs.

Stacked FETS with contact placeholder structures

According to the embodiment of the present invention, a semiconductor device includes a first source/drain and a second source/drain. A first source/drain contact includes a first portion and a second portion. The first portion of the first source/drain contact is located directly atop the first source/drain. The second portion of the first source/drain contact extends vertically past the first source/drain. The first source/drain is in direct contact with three different sides of a first section of the second portion of the first source/drain contact.

Via to backside power rail through active region

In an approach, a processor receives device identification information corresponding to at least one device local to a location of a transaction. A processor receives notification of an infected user. A processor determines that the infected user is associated with the transaction. A processor identifies a second user from the device identification information. A processor sends a notification to the second user.

Contact tracing utilizing device signatures captured during transactions

Provided is a semiconductor device. The semiconductor device comprises a transistor comprising a plurality of source/drain epitaxies. The semiconductor device further comprises at least one backside power rail under the transistor. The semiconductor device further comprises a backside inter-layer dielectric (ILD) located between the plurality of source/drain epitaxies and the at least one power rail. The semiconductor device further comprises a first backside contact connecting a first source/drain epitaxy to the at least one backside power rail. The semiconductor device further comprises one or more contact placeholders formed under the other source/drain epitaxies.

Self-aligned backside contact integration for transistors

Embodiments are disclosed for a method. The method includes generating a correction datastore indicating shifts in magnitude representing corresponding characters that uniquely identify hardware comprising a computer processing chip. The method further includes generating security masks based on a correction file. Additionally, the method includes using a correction process for the computer processing chip. The generated security masks include corresponding overlays representing the shifts in magnitude with respect to corresponding product masks for the computer processing chip. The method also includes generating the computer processing chip using the security masks and the product masks.

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Albany, NY, United States of America

Nikhil Jain