Cadence Design Systems, Inc.

Nikhil Garg

Chandra Prakash Manglani

Subhashis Mandal

Kanaka Raju Gorle

Henry K Yu

Karun Sharma

Sachin Shrivastava

Preeti Kapoor

Sravasti Gupta Nair

Ankur Chaplot

Yashu Gupta

Juno Jui-Chuan Lin

Michaela Guiney

Sankalp Srivastava

An approach is described for a method, system, and product, the approaching includes identification of an integrated circuit design, identification of sync groups (nets having synchronous voltage levels), generation of a physical design having sync group constraints, and performance of design rule checking on a physical design based on at least transferred sync group information. This provides for performing design rule analysis at least using small minimum spacing requirements then would otherwise be required with prior techniques. In some embodiments, the approach includes a verification process that ensures that synchronous voltage behavior is appropriately associated with members of respective sync groups and cleans up old association data that is no longer relevant/correct.

Method, system, and product for generating and maintaining a physical design for an electronic circuit having sync group constraints for design rule checking

A method including creating a plurality of component groups in a circuit layout coupling multiple components in each component group of the plurality of component groups with a power rail, a ground rail, or a bulk, is provided. The method includes creating internal clusters based on a group cost and including the group cost in an overall cost function, forming a gap between two component groups of the plurality of component groups, and filling the gap with a first gap cell adjacent to a first power rail and to a first ground rail, and a second gap cell adjacent to the first gap cell. A system and a non-transitory, machine readable medium storing instructions to perform the above method are also provided.

Power domain placement of circuit components in advance node custom design

Disclosed are techniques for implementing routing aware placement for an electronic design. These techniques identify a block having one or more first pins or interconnects to be inserted into a first layer corresponding to a first set of tracks and identify a second set of tracks on a second layer adjacent to the first layer. One or more candidate locations may be generated on the first layer for the block based in part or in whole upon the first set of tracks. The block may be inserted into a candidate location on the first layer based in part or in whole upon respective costs or routability of the one or more candidate locations with respect to the second set of tracks.

Method, system, and computer program product for implementing routing aware placement for an electronic design

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Faridabad, India

Nikhil Garg