Marvell Asia Pte., Ltd.

Nikhil Bernard John Stephen

Ulf Hanebutte

Senad Durakovic

Chien-Chun Chou

Pranav Jonnalagadda

A method includes receiving a machine learning (ML) network model in high-level code; generating an internal representation (IR), the IR is mapped to components in a multi-processing tile device; determining whether a first processing tile with a first on-chip memory (OCM) has a same dimension for an input/output tensor data as a second processing tile with a second OCM performing a same primitive function based on the IR; allocating a same memory address range within the first and the second OCM for the same primitive function if the first processing tile has the same dimension for the input/output tensor data as the second processing tile for the same primitive function; linking the memory address range of the first OCM to the memory address range of the second OCM to form a grouped memory space within the first and the second OCM respectively; and compiling low-level instructions based on the linking.

Growing community of inventors

Sunnyvale, CA, United States of America

Nikhil Bernard John Stephen