Netlogic Microsystems, Inc

Apple Inc.

Invensense, Inc.

Nikhil Acharya

Stefanos Sidiropoulos

Dean Liu

Marc Loinaz

R Shekhar Narayanaswami

Stanley B Wang

Sunmin Jang

Hari P Paudel

Shengzhe Jiao

Hopil Bae

Seung Bum Rim

Chen Chen

Mahdi Farrokh Baroughi

Wei Xiong

Henry C Jen

Xiang Lu

Majid Gharghi

Stanley Bo-Ting Wang

Young Don Bae

Pablo Moreno Galbis

Haitao Li

Feng Yu

Yaser Azizi

Yongjie Jiang

Ce Zhang

Dongwon Kwon

R Sekhar Narayanaswami

Jeongsup Lee

Pruthvi Chaudhari

SeyedAli TaheriTari

Jialin Liu

Arjunsimha Chaturbhuj

Ruofan Zhang

A display system may include a plurality of light emitting diodes to emit light, where each of the light emitting diodes are connected in parallel and a plurality of first switches respectively coupled to the plurality of light emitting diodes. A first switch of the plurality of first switches is coupled in parallel to a first light emitting diode. The first switch may short the first light emitting diode of the plurality of light emitting diodes through a defined resistor having a defined value that therefore draws a defined short circuit current.

Systems and methods for mitigating micro-LED failures

Electronic devices, displays, and methods are provided for operating an electronic display in coexistence with sensors that could be adversely impacted by the operation of the electronic display. An electronic device may include an electronic display and a sensor. The electronic display may display image content by light emission during an emission period and periodically enter a quiet period in which the light emission of the electronic display is turned off. The sensor may perform sensing operations during the quiet period without interference from the operation of the electronic display.

Electronic display timing to mitigate image artifacts or manage sensor coexistence

A device includes a plurality of high voltage cells (HVC) coupled to a plurality of resistors, and a controller. The plurality of HVC generates an output voltage that is higher than an input voltage to the plurality of HVC. The controller receives a reference voltage and an output voltage from a resistor of the plurality of resistors. The controller generates a signal responsive to a difference between the reference voltage and the output voltage. The controller forms a closed feedback loop with the plurality of HVC and the plurality of resistors. The generated signal is input to the plurality of HVC. A substrate of a resistor of the plurality of resistors is biased to an output of at least one high voltage cell of the plurality of HVC. Output of the at least one high voltage cell is input to another high voltage cell.

High voltage circuitry with drift mitigation

A frequency synthesis circuit includes a phase locked loop and an interpolator circuit. The phase locked loop circuit receives a reference clock and a feedback clock and generates an output clock with a frequency based on the reference clock and the feedback clock. An interpolator circuit is coupled in the feedback path of the phase locked loop circuit. An interpolator control circuit generates an interpolator control word that specifies a variable time delay for the interpolator circuit. The interpolator circuit receives the output clock, and generates the feedback clock by introducing a variable time delay in the output clock in accordance with the interpolator control word. The time variable delay varies the frequency of the output circuit. Embodiments for frequency synthesis circuits that include a spread spectrum frequency clock generator, frequency modulators, and a fixed frequency clock generator circuit are disclosed.

Methods and apparatus for frequency synthesis with feedback interpolation

Methods and apparatus for minimizing jitter in a clock synthesis circuit that uses feedback interpolation

Methods and apparatus for generating multiple clocks using feedback interpolation

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Mountain View, CA, United States of America

Nikhil Acharya