Micron Technology Incorporated

Nikesh Agarwal

Robert Michael Walker

Provided is a system comprising a communication interface between a host and a device, wherein the header of a first memory request transmitted on the forward link of the communication interface encodes, in a bit vector, addresses to be read for a plurality of second memory requests. Combining one or more read requests with another request such that a single request header is transmitted for a plurality of respective requests provides for more efficient use of the forward link bandwidth. Corresponding methods are also described.

Combining read requests having spatial locality

In a computer host system, a system and method to compress the transmission between the central processing unit (CPU) and the dynamic random access memory (DRAM) of either of an extended consecutive series of '0' bits or an extended consecutive series of ‘1’ bits. The CPU or a Compute Express Link (CXL) Initiator associated with the CPU identifies the consecutive strings of ‘0’ bits or ‘1’ bits. The CPU or the CXL Initiator sets data flags in a FLIT data structure, using just two bits or four bits to indicate the strings. The data structure is sent to a CXL memory, which interprets the flags and constructs the extended series of ‘0’ bits or extended series of ‘1’ bits.

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Boise, ID, United States of America

Nikesh Agarwal