Sandisk Technologies Inc.

Western Digital Technologies, Inc.

Nika Yanuka

Eran Sharon

Idan Alrod

Alexander Bazarsky

Ariel Navon

Dudy David Avraham

Ran Zamir

Yoav Weinberg

Daniel Joseph Linnen

Preston Allen Thomson

Karin Inbar

Omer Fainzilber

Stella Achtenberg

Kirubakaran Periyannan

Tomer Tzvi Eliash

Evgeny Mekhanik

Tsiko Shohat Rozenfeld

James Tom

A storage system has an inference engine that can infer a read threshold based on a plurality of parameters of the memory. The read threshold can be used in reading a wordline in the memory during a regular read operation or as part of an error handling process. Using a machine-learning-based approach to infer a read threshold can provide significant improvement in read threshold accuracy, which can reduce bit error rate and improve latency, throughput, power consumption, and quality of service. In another embodiment, a circuit-bounded array is used to manage updates to time and temperature tag information and to infer read thresholds.

Storage system and method for circuit-bounded-array-based time and temperature tag management and inference of read thresholds

For bit errors caused by intrinsic cell variations, the bit errors are scattered across a page of memory. However, for bit errors caused by a physical issue in memory, the bit errors cluster together within the same memory area. In an example data storage device, a page of memory is divided into sections, and counters are used to count the number of errors in each section. A physical error location is detected if the number exceeds a parameter, and as compared to the number of errors in the other sections. In another example data storage device having an error correction code (ECC) engine, a histogram and binomial probability are used to detect physical errors. This has the advantage of detecting weak memory blocks that are about to fail, so the blocks can be retired early as a grown bad block.

Data storage device and method for identifying a failing area of memory based on a cluster of bit errors

A storage system has an inference engine that can infer a read threshold based on a plurality of parameters of the memory. The read threshold can be used in reading a wordline in the memory during a regular read operation or as part of an error handling process. Using this machine-learning-based approach to infer a read threshold can provide significant improvement in read threshold accuracy, which can reduce bit error rate and improve latency, throughput, power consumption, and quality of service. In another embodiment, a storage system is configured to use a binary full-depth symmetrically-sorted tree to infer a read threshold based on a plurality of parameters of the memory.

Storage system and method for implementation of symmetric tree models for read threshold calibration

A storage system has an inference engine that can infer a read threshold based on a plurality of parameters of the memory. The read threshold can be used in reading a wordline in the memory during a regular read operation or as part of an error handling process. Using this machine-learning-based approach to infer a read threshold can provide significant improvement in read threshold accuracy, which can reduce bit error rate and improve latency, throughput, power consumption, and quality of service.

Storage system and method for inference of read thresholds based on memory parameters and conditions

A system and method for calibrating read threshold voltages includes performing a plurality of read operations, determining to perform a read level tracking method, and performing the read level tracking method. The determining may be based on a temperature change or a bit error rate (BER). The read level tracking method includes determining the BER of an indicative word line, determining an adjusted read threshold level based on the BER, and adjusting read threshold levels according to the adjusted read threshold level.

Read threshold calibration for cross-temperature long, sequential reads

Apparatuses, systems, methods, and computer program products are disclosed for seed generation. An apparatus includes a memory element. An apparatus includes a scrambler component. A scrambler component includes a random seed generation circuit that generates a random seed. A scrambler component includes a deterministic seed generation circuit that generates a deterministic seed based on a physical address of a memory element for storing data. A scrambler component includes a computation circuit that forms a computed seed based on a random seed and a deterministic seed. Data is scrambled using a computed seed before data is stored.

Seed generation

Growing community of inventors

Hadera, Israel

Nika Yanuka