Mitsubishi Denki Kabushiki Kaisha

Renesas Technology Corp.

Niichi Itoh

Tetsuya Watanabe

Yasunobu Nakase

Chikayoshi Morishima

A clock signal transmission line in the semiconductor integrated circuit device includes a plurality of straight portions arranged side by side in a predetermined direction and a plurality of bent portions connecting the respective straight portions. At least two of a plurality of signal lines to which a clock signal is transmitted are connected to different straight portions. Consequently, a semiconductor integrated circuit device which can reduce a clock skew when transmitting a clock signal to a plurality of signal lines is provided.

Semiconductor integrated circuit device having clock signal transmission line and wiring method thereof

A clock generator () outputs either a first clock signal or a second clock signal. The second clock signal is higher in frequency than the first clock signal. Under control of a control signal (CNTL), when the first clock signal and the second clock signal are outputted from the clock generator (), a selector () transmits the first and second clock signals to a clock transmission line () and to a clock transmission line (), respectively. The clock transmission line () is greater in linewidth than the clock transmission line (). Under control of the control signal (CNTL), a selector () connects either the clock transmission line () or the clock transmission line () to the outside.

Clock signal transmission circuit

A semiconductor device is provided with dummy patterns at an originally thinner portion of each of layers, and each of these dummy patterns is electrically connected to a reference wire that is either a power-supply wire or a ground wire.

Semiconductor device, designing method and designing device thereof

Provided is a semiconductor memory having a layout structure in which a memory cell has excellent patterning controllability. A pattern of element components (active regions,to,and,to,and polysilicon regions,to,) of a memory cell for one memory cell unit of a memory cell array region,is identical to that of a dummy cell of a peripheral dummy cell region,and both patterns present a line symmetrical relationship with respect to a boundary line BC,In addition, a pattern of the memory cell for one memory cell unit of the memory cell array region,is identical to that of a dummy cell of a power wiring region,and both patterns present a line symmetrical relationship with respect to a boundary line BC

Semiconductor device

A wiring-capacitance improvement aid device aiding in eliminating a capacitance-attributable error of layout data generated by an automatic arrangement and routing tool includes a subject-net extraction portion extracting a subject net with a capacitance-attributable error, a network rip-up portion ripping up a cell netted within a predetermined range with respect to a subject net extracted by the subject-net extraction portion, and a constraint imposition portion imposing a wiring-capacitance constraint on a net connected to a cell ripped up by the network rip-up portion.

Wiring-capacitance improvement aid device aiding in improvement of points having wiring-capacitance attributable error only with layout modification, method thereof, and medium having a program therefor recorded therein

A precharge circuit and a bit line load circuit are provided to a read bit line pair. The bit line load circuit continuously supplies a prescribed current to a read bit line. When data is written to one of memory cells selected in common by one read word line, the level of each read bit line will not be lowered to the level of the ground potential by the bit line load circuit if a read word line is activated, and therefore the loads of both discharge and charge operations by transistors in the memory cell are reduced.

Semiconductor memory device permitting time required for writing data to be reduced

Provided is a semiconductor memory having a layout structure in which a memory cell has excellent patterning controllability. A pattern of element components (active regions 10 to 15 and 21 to 23 and polysilicon regions 31 to 42) of a memory cell for one memory cell unit of a memory cell array region 1 is identical to that of a dummy cell of a peripheral dummy cell region 3, and both patterns present a line symmetrical relationship with respect to a boundary line BC1. In addition, a pattern of the memory cell for one memory cell unit of the memory cell array region 1 is identical to that of a dummy cell of a power wiring region 2, and both patterns present a line symmetrical relationship with respect to a boundary line BC2.

Growing community of inventors

Hyogo, Japan

Niichi Itoh