Dell Products Inc.

Nihit S Bhavsar

Timothy Michael Lambert

Jeffrey Leighton Kennedy

Michael Joseph Stumpf

Jordan Chin

A method may include, during a first initial boot of a management controller, writing baseline processor domain status information associated with boot of each of a main processor and a second processor of the management controller to a baseline queue, and during each subsequent boot of the management controller, writing run-time processor domain status information associated with boot of each of the main processor and the second processor to a run-time queue, determining if a deviation exists between the run-time queue and the baseline queue, and responsive to the deviation existing between the run-time queue and the baseline queue, taking one or more responsive actions.

Multi-domain boot and runtime status code drift detection

An information handling system may include a motherboard and a floating paddle card. The motherboard may include a host system comprising a host system processor, a logic device configured to perform a functionality of the information handling system in accordance with code stored on non-transitory computer-readable media of the logic device, and a management controller communicatively coupled to the host system processor and the logic device and configured to perform out-of-band management of the information handling system. The floating paddle card may be communicatively coupled to the motherboard and configured to serve as interface between one or more devices coupled to the floating paddle card and the logic device and the management controller, the floating paddle card comprising a microcontroller unit configured to, alone or in combination with other circuitry of the floating paddle card, divide management of the one or more devices between the motherboard and the floating paddle card.

Systems and methods for floating paddle card enablement

An information handling system may include a memory comprising a plurality of memory modules, each memory module comprising a plurality of memory chips, a host system comprising a host system processor configured to, during a boot of the information handling system, execute a basic input/output system of the information handling system configured to monitor for one or more faults of one or more memory modules of the plurality of memory modules, and control circuitry. The control circuitry may be configured to, in response to the one or more faults, determine if, all of one or more memory modules associated with a power control signal of such one or more memory modules have experienced faults, and if all of the one or more memory modules associated with the power control signal have experienced faults, de-assert the power control signal such that the one or more memory modules are de-energized.

Systems and methods for power protection on failed memory devices

An information handling system may include an air mover configured to drive a flow of air and a processing component communicatively coupled to the air mover for controlling operation of the air mover via a first wire configured to communicate analog air mover speed commands from the processing component to the air mover for controlling a speed of the air mover and a second wire configured to communicate analog tachometer information from the air mover to the processing component. At least one of the air mover and the processing component may be configured to initiate a mode for serial digital communication via the first wire and the second wire. The air mover and the processing component may be configured to communicate information to each other in accordance with a digital communication protocol via the first wire and the second wire during the mode for serial digital communication.

Communication with an information handling system air mover using enhanced data-over-tachometer signal protocol with variable read and write commands

A method may include providing a first pulse width modulation (PWM) signal to a microcontroller unit (MCU) included at a cooling fan. The method may further include receiving information from the MCU identifying a duty cycle of a second PWM signal generated by the MCU, the duty cycle of the second PWM signal determined by the MCU based on a duty cycle of the first PWM signal and based on a tachometer signal received from a rotor included at the cooling fan. The present current consumption of the cooling fan may be determined based on the duty cycle of the second PWM signal.

Method for monitoring cooling fan performance and system therefor

An information handling system includes a processor with an Improved Inter-Integrated Circuit (I3C) master interface, a first device with a first I3C slave interface, and a second device with a second I3C slave interface. The first I3C slave interface provides first In-Band Interrupts (IBIs) to the I3C master interface and has a first I3C address. The second I3C interface provides second IBIs to the I3C master interface and has a second I3C address. The second I3C address is higher than the first I3C address. The processor receives the first IBI, determines that the second IBIs are masked by the first Mb due to the second I3C address being higher than the first I3C address, and assigns a third I3C address to one of the first I3C slave interface and the second I3C slave interface in response to determining that the second IBIs are masked by the first IBIs.

System and method for overcoming in-band interrupt starvation with dynamic address remapping

A multiplexor for an I3C) network includes a switch, a routing map, and an interrupt detector. The switch selectably couples I3C slave interfaces to I3C master interfaces. The routing map includes map entries associating each I3C slave interface with an I3C master interfaces based upon an I3C address of the I3C slave interface, such that, for each map entry, an IBI received from the associated I3C slave interface is mapped to the associated I3C master interface. The interrupt detector detects an IBI from an I3C slave interface, determines that a map entry associated with the I3C slave interface maps the I3C slave interface with a particular I3C master interface based upon the IBI, and directs the switch to couple the I3C slave interface to the I3C master interface based upon the map entry.

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Round Rock, TX, United States of America

Nihit S Bhavsar