Xilinx, Inc.

Nihat E Tunali

Christopher H Dick

Raied N Mazahreh

Richard Lewis Walke

Hai-Jo Tarn

Michael Wu

Raghavendar Mysore Rao

Krishna Rama Narayanan

Andrew M Whyte

Andrew Dow

A decoder circuit includes a low-density parity-check (LDPC) repository, an LDPC code configurator, and LDPC decoding circuitry. The LDPC repository stores parity-check information associated with one or more LDPC codes. The LDPC code configurator may receive a first LDPC configuration describing a parity-check matrix for a first LDPC code and may update the parity-check information in the LDPC repository to reflect the parity-check matrix for the first LDPC code. The LDPC decoding circuitry may receive a first codeword encoded in accordance with the LDPC code. More specifically, the LDPC decoding circuitry may be configured to read the parity-check information associated with the first LDPC code from the LDPC repository and iteratively decode the first codeword using the parity-check information associated with the first LDPC code.

User-programmable LDPC decoder

A decoder circuit includes a low-density parity-check (LDPC) repository to store parity-check information associated with one or more LDPC codes and an LDPC code configurator to receive a first LDPC configuration describing a parity-check matrix for a first LDPC code and to update the parity-check information in the LDPC repository to reflect the parity-check matrix for the first LDPC code. The decoder circuit further includes an LDPC decoder circuitry configurable, based on control signals, to perform LDPC decoding of codewords or LDPC encoding of information using the parity-check information from the LDPC repository.

Low-density parity-check (LDPC) encode using an LDPC decoder

A decoder circuit includes an input configured to receive an encoded message generated based on a QC-LDPC code. A first layer process unit is configured to process a first layer of a parity check matrix to generate a plurality of log-likelihood ratio (LLR) values corresponding to a plurality of variable nodes associated with the encoded message respectively. The first layer process unit includes a plurality of row process units configured to process a first plurality of rows of the first layer in parallel to generate a plurality of row update values. A layer update unit is configured to generate a first LLR value for a first variable node using first and second row update values for the first variable node. An output is configured to provide a decoded message generated based the plurality of LLR values.

Systems and methods for decoding quasi-cyclic (QC) low-density parity-check (LDPC) codes

Methods and systems are presented in this disclosure for implementing forward error correction in cloud and data center storage devices based on low-density parity-check (LDPC) channel coding. A forward error correction circuit presented herein includes a first LDPC decoder configured to perform hard-decision LDPC decoding of data read from a storage medium through a first read channel. The forward error correction circuit further includes a hybrid LDPC decoder selectively configurable to perform a selected one of hard-decision LDPC decoding and soft-decision LDPC decoding of data read from the storage medium through a second read channel, wherein, responsive to a control signal generated based, at least in part, on one or more parameters indicative of condition of the storage medium, the hybrid LDPC decoder is switchable between hard-decision LDPC decoding and soft-decision LDPC decoding.

Hybrid architecture for LDPC channel coding in data center

A method includes receiving frequency domain (FD) symbols associated with data symbols transmitted in a channel on a frame including a plurality of subcarriers and a plurality of time-slots. An equalization process is performed to the received FD symbols to generate FD equalized symbols. The FD equalized symbols is transformed to time domain (TD) symbols. A demodulation process is performed to the TD symbols to provide estimates of the data symbols.

Generalized frequency division multiplexing (GFDM) multiple-input multiple-output (MIMO) system

A method includes communicating data in a channel. Received symbols for the data correspond to points of a received symbol space respectively. First and second dimensions of the received symbol space correspond to a real part and an imaginary part of the received symbols respectively. A first received symbol for the data is obtained. A first region of the received symbol space for the first received symbol is determined. A first regression model associated with the first region and a first bit of the first received symbol is retrieved from a storage. The first regression model includes a plurality of regressors. A first log-likelihood ratio (LLR) for the first bit of the first received symbol is estimated using the first regression model.

System and method for computing log likelihood ratios

A system for providing data encoding includes: an encoder configured to encode message data with an encoding parity-check matrix having a parity part that is in lower-triangular form to generate an encoded message data, the encoded message data being for decoded by a decoder; wherein the encoding parity-check matrix is based on a decoding parity-check matrix that does not comprise any degree-1 node in a parity part of the decoding parity-check matrix; and wherein the system further comprises a non-transitory medium for storing the encoding parity-check matrix, wherein the non-transitory medium is a part of the encoder or is communicatively coupled to the encoder.

Efficient low error-floor LDPC codes

A method for matrix expansion is disclosed. In this method, a Progressive Edge Growth ('PEG') expanding of an H matrix by a coder is used to provide an expanded H matrix. An Approximate Cycle Extrinsic Message Degree ('ACE') expanding of the expanded H matrix by the coder is used to provide a parity check matrix for a code. The ACE expanding includes initializing a first index to increment in a first range associated with a PEG expansion factor, expanding each non-zero element in the expanded H matrix with a random shifted identity matrix for the first range, initializing a second index to increment in a second range associated with the first index and an ACE expansion factor, and performing an ACE detection for each variable node in the second range for the variable nodes of the parity check matrix. The coder outputs information using the parity check matrix.

Matrix expansion

An apparatus is disclosed. In this apparatus, at least one coder block has a parity check matrix. The parity check matrix comprises each element of an H matrix expanded by a Progressive Edge Growth ('PEG') expansion factor and an Approximate Cycle Extrinsic Message Degree ('ACE') expansion factor.

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Campbell, CA, United States of America

Nihat E Tunali