Qualcomm Incorporated

Nigel Terence Poole

Andrew Evan Gruber

Avinash Seetharamaiah

Thomas Edwin Frisinger

Vijay Kumar Donthireddy

Anirudh Rajendra Acharya

Colin Christopher Sharp

Jonnala Gadda Nagendra Kumar

Srihari Babu Alla

Murat Balci

David Rigel Garcia Garcia

Jian Liang

Zilin Ying

Richard Hammerstone

Hitendra Mohan Gangani

Vishwanath Shashikant Nikam

Eduardus Antonius Metz

Xuefeng Tang

Abhiraj Deshpande

Tushar Garg

Xuhui Mao

Joohi Mittal

Eduardus A Metz

A graphics processor may obtain an indication of at least one state update from at least one CP associated with a graphics processor, where the at least one state update corresponds to one or more states in a set of states associated with the graphics processor. The graphics processor may determine whether the one or more states are stored in a cache associated with the graphics processor. The graphics processor may discard the at least one state update based on a determination that the one or more states are stored in the cache or update the cache based on a determination that the one or more states are not stored in the cache.

Elimination cache

Systems, methods, and computer-readable media are provided for signing and executing graphics processing unit (GPU) commands. In some examples, a method can include receiving, by a GPU, one or more commands including one or more verification signatures generated using a processor, each verification signature of the one or more verification signatures including a first value generated based on the one or more commands; generating, by the GPU, one or more additional verification signatures associated with the one or more commands, wherein each verification signature of the one or more additional verification signatures includes a second value generated by the GPU based on the one or more commands; and determining, by the GPU, a validity of the one or more commands based on a comparison of the one or more verification signatures and the one or more additional verification signatures.

Signed command stream and command execution

The present disclosure relates to methods and devices for graphics processing including an apparatus, e.g., a GPU. The apparatus may process a first workload of a plurality of workloads at each of multiple clusters in a GPU pipeline. The apparatus may also increment a plurality of performance counters during the processing of the first workload at each of the multiple clusters. Further, the apparatus may determine, at each of the multiple clusters, whether the first workload is finished processing. The apparatus may also read, upon determining that the first workload is finished processing, a value of each of the multiple clusters for each of the plurality of performance counters. Additionally, the apparatus may transmit an indication of the read value of each of the multiple clusters for all of the plurality of performance counters.

Performance overhead optimization in GPU scoping

Deferred command execution by a command processor (CP) may be performed based on a determination that at least one command of a primary buffer is located between a first link of the primary buffer and a second link of the primary buffer. The first link and the second link may be to one or more secondary buffers that includes a set of commands. The CP may initiate, before executing, a fetch of a first set of commands in the set of commands based on the first link, a fetch of the at least one command of the primary buffer, and a fetch of a second set of commands in the set of commands based on the second link. After initiating the fetch of the second set of commands, the CP may execute the first set of commands, the at least one command of the primary buffer, and the second set of commands.

Deferred command execution

The present disclosure relates to methods and apparatus of operation of a processing unit. The apparatus can update a first context register of one or more context registers based on a first programming state. In some aspects, the one or more context registers can be associated with at least one processing unit cluster in a graphics processing pipeline of the processing unit. The apparatus can execute a first draw call function corresponding to the first programming state. The apparatus can determine whether at least one additional first draw call function corresponds to the first programming state. In some aspects, the at least one additional first draw call function can follow the first draw call function in the graphics processing pipeline. Also, the apparatus can execute the at least one additional first draw call function when the at least one additional first draw call function corresponds to the first programming state.

Methods and apparatus for GPU context register management

The techniques of this disclosure include deferred batching of incremental constant loads. Graphics APIs include the ability to use lightweight constants for use by shaders. A buffer is allocated by a graphics processing unit (GPU) driver that contains a snapshot of the current lightweight constants. This may provide a complete set of state to serve as a starting point. From then on updates to the lightweight constants may be appended to this buffer in an incremental fashion by inserting the update and increasing the size of the buffer by a command processor on a graphics processing unit (GPU). The incremental nature of the updates may be captured, but removes the need for issuing them on every draw call and instead the incremental updates may be batch processed when a live draw call is encountered.

Deferred batching of incremental constant loads

A method of data processing, the method comprising receiving, at a graphics processing unit (GPU), a command stream, the command stream including one or more commands to be performed by the GPU and at least one command stream marker, the at least one command stream marker indicating a workload type of the command stream, determining, by the GPU, an operation algorithm for the GPU based on the at least one command stream marker prior to executing the command stream, and executing, by the GPU, the command stream based on the operation algorithm.

GPU operation algorithm selection based on command stream marker

This disclosure is directed to deferred preemption techniques for scheduling graphics processing unit (GPU) command streams for execution on a GPU. A host CPU is described that is configured to control a GPU to perform deferred-preemption scheduling. For example, a host CPU may select one or more locations in a GPU command stream as being one or more locations at which preemption is allowed to occur in response to receiving a preemption notification, and may place one or more tokens in the GPU command stream based on the selected one or more locations. The tokens may indicate to the GPU that preemption is allowed to occur at the selected one or more locations. This disclosure further describes a GPU configured to preempt execution of a GPU command stream based on one or more tokens placed in a GPU command stream.

Deferred preemption techniques for scheduling graphics processing unit command streams

Systems, methods, and apparatus for performing queries in a graphics processing system are disclosed. These systems, methods, and apparatus may be configured to read a running counter at the start of the query to determine a start value, wherein the running counter counts discrete graphical entities, read the running counter at the end of the query to determine an end value, and subtract the start value from the end value to determine a result.

Growing community of inventors

Newton, MA, United States of America

Nigel Terence Poole