Digital Equipment Corporation

Cabletron Systems, Inc.

Top Layer Networks, Inc.

Nigel T Poole

Barry A Spinney

George Varghese

Hugh M Wilkinson, Iii

Richard L Szmauz

Scott William Nolan

Theodore L Ross

Krishna Narayanaswamy

Joseph H Brown, Iv

Ronald Salett

A process and system for flexibly switching connections of data packet flows between nodes of data processing system networks by dividing data packets into cells and logically linking these cells on multiple queues of linked pointer lists.

System and process for flexible queuing of data packets in network switching

A bi-directional full duplex clocked bus including eight data lines, a clock line and a control line. The bus signals are low level differential with suitable drivers and receivers. The bus operation includes a protocol of sending groupings of eight bytes transmissions where a byte is sent on the rising and the falling edges of the clock signal. When reading the received data, delayed clocks are used that are formed at the center of both of the received clock signal phases. The delayed clocks may be used to output data on the outputs lines. The delayed clocks are arranged to be symmetrical with substantially no skew and centered to the phases of the received clock signal.

High-speed data bus for network switching

A process and system for switching connections of data packet flows between nodes of data processing system networks operating on diverse protocols according to the application layer information on the data packets.

System and process for application-level flow connection of data processing networks

An apparatus and method for receiving time skewed data from a parallel data bus. A data transfer on the parallel data bus is preceded by a start-of-cell delimiter consisting of a predetermined sequence of pulses on each of the data signals. The data is received from the bus by receive logic employing a local clock. Sampling logic is used to sample each of the data signals received from the bus at a rate which is higher than the local clock rate. Sample registers store a plurality of samples of corresponding data signals, the number of samples stored being large enough to store at least some of the pulses constituting the start-of-cell delimiter. Start-of-cell detect and center select logic is used for determining that a start-of-cell delimiter is stored in each of the sample registers, and for determining which of the samples stored in each of the sample registers represents the approximate center sample of one of the pulses of the start-of-cell delimiter. These center samples correspond to the data signals on the bus, but are de-skewed and synchronous with the local clock.

Method and apparatus for recovery of time skewed data on a parallel bus

Aspects of the invention include a method of conducting a reduced length search along a search path. A node which would otherwise occur between a previous and a following node in the search path is eliminated, and information is stored as to whether, had said eliminated node been present, the search would have proceeded to the following node. During the search, a search argument is compared with the stored information, and the search effectively progresses from the previous node directly to the following node if the comparison is positive. In preferred embodiments, some nodes provide result values for the search, and a node is eliminated only if its presence would not affect the result value for the search. In another aspect, the invention features a method of conducting a two mode search of reduced length. For a first mode of the search, nodes along a search path are provided, at least some of the nodes including one or more pointers pointing to other nodes. A search argument comprising a series of search segments is provided, some values of segments of the argument corresponding to nodes along the search path, some other values of the segments relating to a second mode of the search. Indicators associated with nodes are provided, each indicator indicating the segments corresponding to the second mode. The search path is searched by processing successive search segments by inspecting the indicator associated with each node, and proceeding to the second search mode if the indicator indicates that the segment relates to the second mode.

Compressed prefix matching database searching

A translation is performed by using a programmable hashing technique on an input number to generate a hashed number. A subset of the hashed number bits are used to index a first hash table. In first hash table locations where a hash collision does not occur, the first hash table entry contains an index into an output table which contains the desired translated output number. In first hash table locations where a hash collision occurs, the first hash table entry contains a pointer to a first resolution table area in a second hash table. The first resolution table area contains entries which are indexed by additional bits selected from the hashed number in accordance with a mask field in the first hash table location. If collisions occur in the resolution table a new resolution table is created and the process is repeated. The resolution process thus proceeds in stages until all input numbers have been translated.

Hash-based translation method and apparatus with multiple level

A backplane wiring scheme is provided for use in a hub of a packet data communications system. Line cards are connected to the backplane wiring arrangement in the hub, where each line card is a coupling to a network segment, a station or a to a bridge to other stations or segments. The connection is usually in either a ring or a bus topology, and increased flexibility, reduced power consumption, and easier implementation are provided by a unique wiring scheme. Each line card has a number of receive ports (e.g., N-1) and has two transmit ports, the transmit ports including a transmit-left port and a transmit-tight port. The receive ports and transmit ports are arranged in a regular linear pattern on an edge of each of said line cards. The line cards are inserted in backplane slots, and backplane wiring paths are configured diagonally between ports Of the cards to connect the transmit-left ports of the line cards to receive ports of line cards to the left and to connect the transmit-right ports of the line cards to receive ports of line cards to the tight. When the transmit-left port and the transmit-tight port of each of the line cards are connected together, the line cards are thereby configured as a bus. When only the transmit-left port and a top one of the receive ports are activated for all of the line cards, and the transmit-tight port of only the left-most line card, are activated, the line cards are thereby configured as a ring.

Backplane wiring for hub in packet data communications system

A backplane wiring scheme is provided for use in a hub of a packet data communications system. Line cards are connected to the backplane wiring arrangement in the hub, where each line card is a coupling to a network segment, a station or a to a bridge to other stations or segments. The connection is usually in either a ring or a bus topology, and increased flexibility, reduced power consumption, and easier implementation are provided by a unique wiring scheme. Each line card has a number of receive ports (e.g., N-1) and has two transmit ports, the transmit ports including a transmit-left port and a transmit-right port. The receive ports and transmit ports are arranged in a regular linear pattern on an edge of each of said line cards. The line cards are inserted in backplane slots, and backplane wiring paths are configured diagonally between ports of the cards to connect the transmit-left ports of the line cards to receive ports of line cards to the left and to connect the transmit-right ports of the line cards to receive ports of line cards to the right. When the transmit-left port and the transmit-right port of each of the line cards are connected together, the line cards are thereby configured as a bus. When only the transmit-left port and a top one of the receive ports are activated for all of the line cards, and the transmit-right port of only the left-most line card, are activated, the line cards are thereby configured as a ring.

A method and apparatus for addressing compressed nodes in a database structure is disclosed in which each compressed node is associated with a particular mapping function and each element in the node is assigned a particular identification code. The character to be searched is converted into a physical address having a first portion which is used to index to a particular element in a compressed node, and a second portion which is used to verify that the selected element corresponds to the search character.

Growing community of inventors

Natick, MA, United States of America

Nigel T Poole