Pts Corporation

Altera Corporation

Synopsys, Inc.

Nigel Peter Topham

Adrian Philip Wise

Nicholas Paul Joyce

Jonathan Michael Harris

Kar-Lik Kasim Wong

A processor for executing configurable instructions and a method of configuring the processor are disclosed. In one embodiment, the processor includes (i) a processor core to execute preconfigured instructions and (ii) a processor core extension to execute user-defined extension instructions that are configurable instructions. The user-defined extension instructions may include an autonomous instruction with varying execution cycles based on source data and an operation performed. The processor core extension employs extension interface signals as a handshake protocol to operate together with the processor core without knowing any priori knowledge of how many processor clock cycles that the autonomous instruction will take to complete.

Self-timed user-extension instructions for a processing device

Systolic array-based systems and methods for performing block matching in motion compensation. A target pixel block is loaded into a systolic array. A matching sized block of a reference search space is loaded into the array, row by row. A sum of absolute difference (SOAD) is computed for each row and stored. After each row has been loaded, the reference space is incremented to the next column. After the entire reference space has been searched, the reference block with the smallest SOAD is taken as the motion vector for the target pixel block.

Systolic-array based systems and methods for performing block matching in motion compensation

Techniques are disclosed for handling control transfer instructions in pipelined processors. Such instructions may cause the sequence of subsequent instructions to change, and thus may require subsequent instructions to be deleted from the processor's pipeline. Pre-decode means () are provided for at least partially decoding control transfer instructions early in the pipeline. Subsequent instructions can then be prevented from progressing through the pipeline. The mechanism required to delete unwanted instructions is thereby simplified.

Early resolving instructions

Mapping circuitry () comprises a first candidate output value producing unit () which produces a first candidate output value (Cl) that differs by a first offset value (x) from a received input value (r). During operation of the first candidate output value producing unit () a second candidate output value producing unit () produces a second candidate output value (C) that differs by a second offset value (y) from the received input value (r). One of the first and second candidate output values is within a preselected range of allowable output values and the other is outside that range. An in-range value determining unit () determines which one of the first and second candidate output values is within the range, and an output value selection unit () selects this value as the output value (p) corresponding to the received input value (r).

Mapping circuitry and method comprising first and second candidate output value producing units, an in-range value determining unit, and an output value selection unit

A processor has respective first and second external instruction formats (F, F) in which instructions (add, load) are received by the processor. Each instruction has an opcode (e.g. 1011) which specifies an operation to be executed. Each external format has one or more preselected opcode bits (F:i+1&#x2dc;i+4; F:i+1&#x2dc;i+3) in which the opcode appears. The processor also has an internal instruction format (G) into which instructions in the external formats are translated prior to execution of the operation. A first operation (add) is specifiable in both the first and second external formats (F, F), and a second operation (load) is specifiable in the second external format (F). The first and second operations have distinct opcodes (101, 011) in the second external format. In each of the preselected opcode bits which the first and second external formats have in common (i+1&#x2dc;i+3), the opcodes of the first operation (101) in the two external formats are identical. Such 'congruent' instruction encodings can enable a translation process, for translating the external-format opcode into a corresponding internal-format opcode, without the need to positively identify each individual external-format opcode.

Processor adapted to receive different instruction sets

Instructions of a program are stored in compressed form in a program memory (). In a processor which executes the instructions, a program counter () identifies a position in the program memory. An instruction cache () has cache blocks, each for storing one or more instructions of the program in decompressed form. A cache loading unit () includes a decompression section () and performs a cache loading operation in which one or more compressed-form instructions are read from the position in the program memory identified by the program counter and are decompressed and stored in one of the said cache blocks of the instruction cache. A cache pointer () identifies a position in the instruction cache of an instruction to be fetched for execution. An instruction fetching unit () fetches an instruction to be executed from the position identified by the cache pointer. When a cache miss occurs because the instruction to be fetched is not present in the instruction cache, the cache loading unit performs such a cache loading operation. An updating unit () updates the program counter and cache pointer in response to the fetching of instructions so as to ensure that the position identified by the said program counter is maintained consistently at the position in the program memory at which the instruction to be fetched from the instruction cache is stored in compressed form.

Processor and method for generating and storing compressed instructions in a program memory and decompressed instructions in an instruction cache wherein the decompressed instructions are assigned imaginary addresses derived from information stored in the program memory with the compressed instructions

A processor has respective first and second external instruction formats (F, F) in which instructions (add, load) are received by the processor. Each instruction has an opcode (e.g. 1011) which specifies an operation to be executed. Each external format has one or more preselected opcode bits (F: i+1&#x2dc;i+4; F: i+1&#x2dc;i+3) in which the opcode appears. The processor also has an internal instruction format (G) into which instructions in the external formats are translated prior to execution of the operation. A first operation (add) is specifiable in both the first and second external formats F, F), and a second operation (load) is specifiable in the second external format (F). The first and second operations have distinct opcodes (101, 011) in the second external format. In each of the preselected opcode bits which the first and second external formats have in common (i+1&#x2dc;i+3), the opcodes of the first operation (101) in the two external formats are identical.

Instructions of a program are stored in compressed form in a program memory. A cache loading unit includes a decompression section and performs a cache loading operation in which one or more compressed-form instructions are read from the position in the program memory identified by the program counter and are decompressed and stored in one of the said cache blocks of the instruction cache. When a cache miss occurs because the instruction to be fetched is not present in the instruction cache, a cache loading unit performs such a cache loading operation. An updating unit updates the program counter and cache pointer in response to the fetching of instructions so as to ensure that the position identified by the said program counter is maintained consistently at the position in the program memory at which the instruction to be fetched from the instruction cache is stored in compressed form.

Processors comprising a plurality of pipelines are disclosed, each pipeline having a plurality of pipeline stages () for executing an instruction on successive clock cycles. The processors include distributed stall control circuitry () which allow an instruction in one pipeline to become temporarily out of step with an instruction in another pipeline. This may allow time for a global signal, such as a global stall signal, to be distributed.

Stall control

A processor includes a series of predicate registersEach predicate register is switchable between at least respective first and second states and each is assignable to one or more predicated-execution instructions. A control information holding unitholds items of control information which correspond respectively to the predicate registers. An operating unitis provided for each one of the predicate registers and receives items of control information Land Land items of state information P, P. Each operating unit is operable to perform a selected state determining operation in which the state of its own predicate register is determined in dependence upon the received items. The operating units operate in parallel with one another to perform respective such state determining operations. The state determining operations can be used to bring about state changes required in prologue, kernel and epilogue stages of a software-pipelined loop.

Predicated execution of instructions in processors

Renaming registers to values produced by instructions according to assigned produce sequence number

Mapping circuitry ( ) comprises a first candidate output value producing unit ( ) which produces a first candidate output value (C ) that differs by a first offset value (x) from a received input value (r). During operation of the first candidate output value producing unit ( ) a second candidate output value producing unit ( ) produces a second candidate output value (C ) that differs by a second offset value (y) from the received input value (r). One of the first and second candidate output values is within a preselected range of allowable output values and the other is outside that range. An in-range value determining unit ( ) determines which one of the first and second candidate output values is within the range, and an output value selection unit ( ) selects this value as the output value (p) corresponding to the received input value (r).

A processor or processor core has register file circuitry having a plurality of physical registers and a plurality of tag storing portions corresponding respectively to the physical registers. Each tag storing portion stores a tag representing a logical register ID allocated to the corresponding physical register. A register selection unit receives a logical register ID and selects one of the logical registers whose tag matches the received logical register ID. A tag changing unit changes the stored tags so as to change a mapping between at least one logical register ID and one of the physical registers. Such register circuitry permits a mapping between logical register IDs and physical registers to be changed quickly efficiently and can permit a desired physical register to be selected quickly.

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Wokingham, United Kingdom

Nigel Peter Topham