Motorola Corporation

Ford Motor Company Limited

Gentherm Gmbh

Nigel J Allison

Janice L Benzel

Dusko Petrovski

Patrick Jordan

Jay A Hartvigsen

Rand L Gray

Petr Lidak

Joseph F Kowalski

A motor control system configured to detect a pinch condition of a structure actuated by a motor includes a pinch detection module configured to receive a current signal indicative of a motor current, determine a rate of change of current based on the current signal, and generate a pinch signal indicative of the pinch condition in response to either one of the motor current being greater than a current threshold and the rate of change of current being greater than a rate of change threshold. The motor control system further includes a position control module configured to control the motor to actuate the structure in response to an input and at least one of stop and reverse the motor in response to the pinch signal.

Anti-pinch motor control

A system ( ) regulates current and voltage in a power system by using a correction signal that is modified to compensate for errors associated with manufacturing variations. The correction signal controls a power switch ( ) that selectively sources/shunts current to/from the output load ( ) and power source. The compensation technique applies to systems conducting either an A.C. or a D.C. voltage. A current controller ( ) is placed in a control loop. The current controller contains circuitry having an offset voltage and loop gain errors as a result of manufacturing variations. At least one of the offset voltage and loop gain are dynamically calculated by a loop controller ( ) and the result is used to modify the correction signal to provide an accurate output load voltage and power line current.

System and method for regulating a power system with feedback using current sensing

A pin generated interrupt system in a digital data processor is capable of generating interrupt requests in order to awaken the digital data processor from a reduced state of activity and power consumption called stop mode. The user can permanently disable the pin generated interrupt system using a mask option chosen during the manufacturing process. A register bit that determines whether the pin is an input or an output is also used to enable compare circuitry that determines whether an external device is requesting an interrupt. When a plurality of pins are used, it is only necessary for an interrupt to be requested on one of the pins in order for an interrupt request signal to be generated.

Method and apparatus for generating a pin interrupt request in a digital

A method for servicing peripheral interrupt requests in a data processing system is provided. A state vector register stores a current state of a state machine which controls the interrupt-generating peripheral. In addition, the state vector register simultaneously stores an interrupt source identifier, which indicates the source of the highest priority interrupt request currently pending for the interrupt-generating peripheral. When the processor receives an interrupt request, the value stored in the state vector register of the interrupt-generating peripheral is read into an index register in the processor. The processor then uses the value as an index into a jump table, stored in memory, which contains the interrupt service routines. The use of the state vector register in conjunction with existing internal signals enables the processor to rapidly retrieve the appropriate interrupt service routine from memory, while minimizing the system overhead associated with servicing the interrupt request.

Method for servicing a peripheral interrupt request in a microcontroller

In a microcomputer including a CPU and a plurality of modules operatively connected through a main bus including address and data lines, a method of interrupting an operation including providing an interrupt request line and an arbitration bus, and arbitrating between modules and with the CPU on the arbitration bus so that no use of the main bus for arbitration or an interrupt acknowledge are required and the CPU can continue the operation as the arbitration proceeds.

System with modules using priority numbers related to interrupt vectors

A data processing system having a debug peripheral is provided. The debug peripheral is coupled to a central processing unit and memory via an internal communications bus. The debug peripheral is a single-word dual port memory with parallel read-write write access on one side, and synchronous, full-duplex serial read-write access on the other side. The serial side of the debug peripheral is connected to external emulation hardware by means of a three-pin synchronous serial interface. The parallel access is via a connection to a core central processing unit (CPU) internal communications bus. The debug peripheral is addressed at sixteen adjacent locations in the CPU memory space. During a debug interlude, the debug peripheral assumes control of the CPU by providing an interrup signal to the CPU, and thereby causing the CPU to fetch instructions directly from the debug peripheral. The debug peripheral receives instructions from the external emulation hardware, and provides the debug instructions to the CPU, in response to an instruction address provided by the CPU.

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Austin, TX, United States of America

Nigel J Allison