Freescale Semiconductor,inc.

Motorola Corporation

Nigel Graeme Cave

Omar Zia

Terry Grant Sparks

Venkat Kolagunta

Matthew Thomas Herrick

Edward Outlaw Travis, Jr

Ruiqi Tian

Janos Farkas

Kathleen C Yu

Joy Kimi Watanabe

Lawrence Cary Gunn, Iii

Sinan Goktepeli

Srikanth Balaji Samavedam

Byoung W Min

Dharmesh Jawarani

William J Taylor

Michael Rendon

Anna M Phillips

A method for making a semiconductor device is provided which comprises (a) creating a first mask for the epitaxial growth of features in a semiconductor device, said first mask defining a set of epitaxial tiles (); (b) creating a second mask for defining the active region of the semiconductor device, said second mask defining a set of active tiles (); and (c) using the first and second masks to create a semiconductor device.

Integrated assist features for epitaxial growth

A method for making a semiconductor device is provided which comprises (a) creating a first data set () which defines a first set of tiles () for a trench chemical mechanical polishing (CMP) process; (b) deriving a first trench CMP mask set () and a first epitaxial growth mask set () from the first data set, wherein the first epitaxial growth mask set is derived from the first data set by removing a subset () of the tiles defined by the first data set and incorporating the subset of tiles into the first epitaxial growth mask set; and (c) reconfiguring the first trench CMP mask set to account for the first epitaxial growth mask set, thereby defining a second trench CMP mask set ().

Integrated assist features for epitaxial growth bulk tiles with compensation

A method for making a semiconductor device is provided which comprises (a) creating a first data set () which defines a first set of tiles () for a trench chemical mechanical polishing (CMP) process; (b) deriving a first trench CMP mask set () and at least one epitaxial growth mask set () from the first data set, wherein the at least one epitaxial growth mask set corresponds to tiles () present on first () and second () distinct semiconductor surfaces; (c) reconfiguring the first trench CMP mask set to account for the at least one epitaxial growth mask set, thereby defining a second trench CMP mask set (), wherein the second trench CMP mask set defines a set of trench CMP tiles; and (d) using the second trench CMP mask set to make a semiconductor device.

Integrated assist features for epitaxial growth bulk/SOI hybrid tiles with compensation

In a semiconductor device, a relatively deep germanium implant and activation thereof precedes deposition of the nickel for nickel silicide formation. The activation of the germanium causes the lattice constant in the region of the implant to be increased over the lattice constant of the background substrate, which is preferably silicon. The effect is that the lattice so altered avoids formation of nickel disilicide. The result is that the nickel silicide spiking is avoided.

Semiconductor device with silicided source/drains

In one embodiment, a method for forming a semiconductor device is described. A semiconductor substrate has a first portion and a second portion. A first dielectric layer formed over the first portion of the semiconductor substrate and a second dielectric layer is formed over the second portion of the semiconductor substrate. A cap that may include silicon, such as polysilicon, is formed over the first dielectric layer. A first electrode layer is formed over the cap and a second electrode layer is formed over the second dielectric.

Method of forming a semiconductor device and structure thereof

A method for integrating an optical device and an electronic device on a semiconductor substrate comprises forming openings within an active semiconductor layer in a first region of the semiconductor substrate, wherein the first region corresponds to an electronic device portion and the second region corresponds to an optical device portion. A semiconductor layer is epitaxially grown overlying an exposed active semiconductor layer in the second region, the epitaxially grown semiconductor layer corresponding to an optical device region. At least a portion of an electronic device is formed on the active semiconductor layer within the electronic device portion of the semiconductor substrate. The method further includes forming openings within the epitaxially grown semiconductor layer of the optical device portion of the semiconductor substrate, wherein the openings define one or more features of an optical device.

Method of integrating optical devices and electronic devices on an integrated circuit

A semiconductor structure has a waveguide a transistor on the same integrated circuit. One trench isolation technique is used for defining a transistor region and another is used for optimizing a lateral boundary of the waveguide. Both the waveguide and the transistor have trenches with liners that can be separately optimized. The transistor has a salicide for source/drain contacts. During this process, a salicide block is used over the waveguide to prevent salicide formation in unwanted areas of the waveguide. The depth of the trench for the waveguide can be lower than that of the trench for the transistor isolation. Trench isolation depth can be set by an etch stop region that can be either a thin oxide layer or a buffer layer that is selectively etchable with respect to the top semiconductor layer and that can be used as a seed layer for growing the top semiconductor layer.

Via holes to the source/drains of a transistor are made to have very uniform depths so that photoresist thickness can be minimized to reduce the problems associated with small hole vias and vias that are at minimum pitches. This is achieved by polishing a dielectric over the gate stack to a polish stop present over the gate stack to result in having a top surface that is coplanar with the top surface of the polish stop layer over the gate stack. This establishes a top surface that is very uniform in height above the substrate across the wafer. A subsequent dielectric formed on this top surface is thus also very uniform in height over the wafer. The photoresist thickness then can be selected to the least thickness necessary based upon the expectation of maintaining a pattern for etching through a layer of very uniform thickness.

Semiconductor device and method for forming a semiconductor device using post gate stack planarization

In one embodiment, a first dielectric film ( ), and a second dielectric film ( ) are formed over a substrate ( ). The substrate is cured to at least partially change a property of the second dielectric film thereby forming an intermediate etch stop ( ). A third dielectric film ( ) is formed over the substrate ( ). The substrate ( ) is then etched to remove portions of the first dielectric film ( ) and portions of the third dielectric film ( ) using the intermediate etch stop ( ) to form a portion of an interconnect opening ( ). In an alternative embodiment, a resist layer ( ), and portions of an interlevel dielectric layer ( ) are etched. Upon completion of the step of etching, the photoresist layer ( ) and portions of the interlevel dielectric layer ( ) are completely removed.

Method for forming an opening in a semiconductor device substrate

A transistor structure includes a retrograde gate structure ( ) that is narrower at the end that interfaces with the gate dielectric ( ) than it is at the opposite end and method for manufacture of such a structure. The retrograde gate structure ( ) is formed by depositing a layer of gate material ( ) that has varying composition in the vertical direction. The differentiation in composition causes varying lateral etch rate characteristics along the vertical direction of the gate structure ( ) such that increased etching of the gate material ( ) occurs near the interface with the gate dielectric layer ( ).

Transistor with shaped gate electrode and method therefor

In accordance with embodiments of the present invention a trench-level dielectric film ( ) and a via-level dielectric film ( ) are formed overlying a semiconductor device substrate ( ). A via opening ( ) is etched in the trench-level dielectric film with a first etch chemistry that has a higher etch selectivity to the trench-level dielectric film ( ) than to the via-level dielectric film ( ). A trench opening ( ) is patterned in a photoresist layer ( ) overlying the trench-level dielectric film ( ). The via-level dielectric film ( ) is etched with a second etch chemistry to extend the via opening ( ) into the via-level dielectric film ( ). The trench-level dielectric film ( ) is etched to form a trench opening.

Method for forming a semiconductor device

In one embodiment of the invention, conductive support structures (,) are formed within an interlevel dielectric layer. The conductive support structures (,) lie within the bond pad region (,) of the integrated circuit and provide support to portions of the interlevel dielectric layer that have a low Young's modulus. The conductive support structures (,) are formed using the same processes that are used to form metal interconnects in the device region (,) of the integrated circuit, but they are not electrically coupled to semiconductor devices that lie within the device region (,). Conductive support structures (,) are also formed within the scribe line region (,) to provide support to the interlevel dielectric layer in this region of the integrated circuit.

In one embodiment, a first dielectric film (,), and a second dielectric film (,) are formed over a substrate (,). The substrate is cured to at least partially change a property of the second dielectric film thereby forming an intermediate etch stop (,). A third dielectric film (,) is formed over the substrate (,). The substrate (,) is then etched to remove portions of the first dielectric film (,) and portions of the third dielectric film (,) using the intermediate etch stop (,) to form a portion of an interconnect opening (,). In an alternative embodiment, a resist layer (,), and portions of an interlevel dielectric layer (,) are etched. Upon completion of the step of etching, the photoresist layer (,) and portions of the interlevel dielectric layer (,) are completely removed.

Method of forming a semiconductor device

In accordance with embodiments of the present invention a trench-level dielectric film (26) and a via-level dielectric film (24) are formed overlying a semiconductor device substrate (10). A via opening (42) is etched in the trench-level dielectric film with a first etch chemistry that has a higher etch selectivity to the trench-level dielectric film (26) than to the via-level dielectric film (24). A trench opening (54) is patterned in a photoresist layer (52) overlying the trench-level dielectric film (26). The via-level dielectric film (24) is etched with a second etch chemistry to extend the via opening (42) into the via-level dielectric film (24). The trench-level dielectric film (26) is etched to form a trench opening.

In one embodiment of the invention, conductive support structures (112) are formed within an interlevel dielectric layer. The conductive support structures (112) lie within the bond pad region (111) of the integrated circuit and provide support to portions of the interlevel dielectric layer that have a low Young's modulus. The conductive support structures (112) are formed using the same processes that are used to form metal interconnects in the device region (109) of the integrated circuit, but they are not electrically coupled to semiconductor devices that lie within the device region (109). Conductive support structures (114) are also formed within the scribe line region (104) to provide support to the interlevel dielectric layer in this region of the integrated circuit.

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Austin, TX, United States of America

Nigel Graeme Cave