Intel Corporation

Marvell International Limited

Arm Limited

Nigel C Paver

Bradley C Aldrich

Stuart David Biles

Murli Ganeshan

William T Maghielse

Wing K Yu

Jianwei Liu

Moinul H Khan

Mark Norman Fullerton

Yuyun Liao

Anthony Jebson

Deli Deng

Chander Sudanthi

Paul Gilbert Meyer

Daniel Kershaw

Prakash Shyamlal Ramrakhyani

Stephen J Strazdus

Dam Sunwoo

Timothy Charles Mace

Donald Kenneth Felton

Mukesh Patel

Rupal Parikh

Steve J Strazdus

James E Quinlan

Kailesh B Bavaria

Kevin P Welton

James Quinlan

According to some embodiments, a technique provides for the execution of an instruction that includes receiving residual data of a first image and decoded pixels of a second image, zero-extending a plurality of unsigned data operands of the decoded pixels producing a plurality of unpacked data operands, adding a plurality of signed data operands of the residual data to the plurality of unpacked data operands producing a plurality of signed results; and saturating the plurality of signed results producing a plurality of unsigned results.

Residual addition for video software techniques

A data processing apparatus comprising: a data processor for processing data in a secure and a non-secure mode, said data processor processing data in said secure mode having access to secure data that is not accessible to said data processor in said non-secure mode, and processing data in said secure mode being performed under control of a secure operating system and processing data in said non-secure mode being performed under control of a non-secure operating system; and a further processing device for performing a task in response to a request from said data processor, said task comprising processing data at least some of which is secure data; wherein said further processing device is responsive to receipt of a signal to suspend said task to initiate: processing of said secure data using a secure key; and storage of said processed secure data to a non-secure data store; and is responsive to receipt of a signal to resume said task to initiate: retrieval of said processed secure data from said non-secure data store; and restoring of said processed secure data using said secure key; wherein said secure key is securely stored such that it is not accessible to other processes operating in said non-secure mode.

Protecting the security of secure data sent from a central processor for processing by a further processing device

According to some embodiments, a device is configured to perform a dual multiply-accumulate operation. In one embodiment, the device includes a functional unit configured to calculate, in parallel, a first multiplication product of a first coefficient and a first sample; and a second multiplication product of the first coefficient and a second sample. The first sample is an (n)th sample and the second sample is an (n+2)th sample in a plurality of sequential samples. The functional unit outputs and stores the first multiplication product and the second multiplication product in different storage locations in at least one storage device.

Dual-multiply-accumulator operation optimized for even and odd multisample calculations

A data processing system including a plurality of processorseach having a local cache memoryis provided. A cache coherency controllerserves to maintain cache coherency between the local cache memories. When one of the processorsis placed into a low power state its associated local cache memoryis maintained in a state in which the data it is holding is accessible to the cache coherency controlleruntil a predetermined condition has been met whereupon the local cache memoryconcerned is placed into a low power state. The predetermined condition can take a variety of different forms such as the rate of snoop hits falling below a threshold value, the ratio of snooping hits to snoop requests falling below a threshold value, a predetermined number of clock cycles passing since the associated processor for that local cache memory was powered down as well as other possibilities.

Local cache power control within a multiprocessor system

A data processor for processing data in a secure mode having access to secure data that is not accessible to the data processor when processing data in the non-secure mode. A further processing device for performing a task in response to a request from the data processor issued from the non-secure mode. The further processing device including a secure data store not accessible to processes running on the data processor when in the non-secure mode. Prior to issuing requests, the data processor in the secure mode performs a set up operation on the further data processing device storing secure data in the secure data store. In response to receipt of the request from the data processor operating in the non-secure mode, the further data processing device performs the task using data stored in the secure data store to access any secure data required.

Providing secure services to a non-secure application

A cache device is provided for use in a data processing apparatus to store data values for access by an associated master device. Each data value has an associated memory location in a memory device, and the memory device is arranged as a plurality of blocks of memory locations, with each block having to be activated before any data value stored in that block can be accessed. The cache device comprises regular access detection circuitry for detecting occurrence of a sequence of accesses to data values whose associated memory locations follow a regular pattern. Upon detection of such an occurrence of a sequence of accesses by the regular access detection circuitry, an allocation policy employed by the cache to determine a selected cache line into which to store a data value is altered with the aim of increasing a likelihood that when an evicted data value output by the cache is subsequently written to the memory device, the associated memory location resides within an already activated block of memory locations. Hence, by detecting regular access patterns, and altering the allocation policy on detection of such patterns, this enables a reuse of already activated blocks within the memory device, thereby significantly improving memory utilization, thereby giving rise to both performance improvements and power consumption reductions.

Cache device for coupling to a memory device and a method of operation of such a cache device

A data processing system, apparatus and method for performing fractional multiply operations is disclosed. The system includes a memory that stores instructions for SIMD operations and a processing core. The processing core includes registers that store operands for the fractional multiply operations. A coprocessor included in the processing core performs the fractional multiply operations on the operands and stores the result in a destination register that is also included in the processing core.

SIMD processor performing fractional multiply operation with saturation history data processing to generate condition code flags

A data processing system in the form of an integrated circuit includes a general purpose programmable processor and a hardware accelerator. A shared memory management unit provides memory management operations on behalf of both of the processor core and the hardware accelerator. The processor and the hardware accelerator share a memory system. A first communication channel between the processor and the hardware accelerator communicates at least control signals therebetween. A second communication channel coupling the hardware accelerator and the memory system allows the hardware accelerator to perform its own data access operations upon the memory system.

Data processor with hardware accelerator, accelerator interface and shared memory management unit

According to some embodiments, a dual multiply-accumulate operation optimized for even and odd multisample calculations is disclosed.

Dual multiply-accumulator operation optimized for even and odd multisample calculations

A processing systemincluding a memoryand a cache memoryis provided with a page status unitfor providing a cache controller with a page open indication indicating one or more open pages of data values in memory. At least one of one or more cache management operations performed by the cache controller is responsive to the page open indication so that the efficiency and/or speed of the processing system can be improved.

Efficiency of cache memory operations

A data processing apparatusincludes a programmable general purpose processorcoupled to a hardware accelerator. A memory systemis shared by the processorand the hardware accelerator. Memory system monitoring circuitryis responsive to one or more predetermined operations performed by the processorupon the memory systemto generate a trigger to the hardware acceleratorfor it to halt its processing operations and clean any data values held as temporary variables within registersof the hardware accelerator back to the memory system

Controlling cleaning of data values within a hardware accelerator

Methods and apparatus for calculating Single-Instruction-Multiple-Data (SIMD) complex arithmetic. A coprocessor instruction has a format identifying a multiply and subtract instruction to generate real components for complex multiplication of first operand complex data and corresponding second operand complex data, a cross multiply and add instruction to generate imaginary components for complex multiplication of the first operand complex data and the corresponding second operand complex data, an add-subtract instruction to add real components of the first operand to imaginary components of the second operand and to subtract real components of the second operand from imaginary components of the first operand, and a subtract-add instruction to subtract the imaginary components of the second operand from the real components of the first operand and to add the real components of the second operand to the imaginary components of the first operand.

Add-subtract coprocessor instruction execution on complex number components with saturation and conditioned on main processor condition flags

In one embodiment, a method is provided. The method of this embodiment provides monitoring one or more sensor outputs of a sensor, the sensor to measure a power consumption property of the chip, and each sensor output to indicate a measurement of the power consumption property; and recording a time that each of the one or more sensor outputs indicates an existence of the power consumption property at the measurement corresponding to each of the one or more sensor outputs.

Growing community of inventors

Beaverton, OR, United States of America

Nigel C Paver