Promos Technologies, Inc

Mosel Vitelic Corporation

Seimens Aktiengesellschaft

Nien-yu Tsai

Chun-Wei Chen

Joseph Wu

Hong-Long Chang

J S Shiao

Ming-Li Kung

Chen-Wei Chen

A method for forming a bit line of a DRAM memory array is disclosed. The method comprises the steps of: forming an interlayer dielectric over the DRAM memory array; etching the interlayer dielectric to form trenches in the interlayer dielectric, the trenches collectively forming a bit line pattern and having tapered side walls; and depositing a conductive material into the trenches to form the bit line.

Etching method for reducing bit line coupling in a DRAM

A method of forming a metal interconnect structure and via plugs over a dielectric layer having a plurality of vias formed therein is disclosed. The method comprises the steps of: forming tungsten via plugs in the plurality of vias; depositing a metal layer over the dielectric layer and the plurality of tungsten via plugs; patterning and etching the metal layer using a photoresist layer to form the metal interconnect structure; oxidizing the metal interconnect structure and the tungsten via plugs to form a metal oxide layer over the metal interconnect structure and tungsten via plugs; and performing a wet strip on the metal interconnect structure.

Method of forming tungsten interconnect with tungsten oxidation to

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Taipei, Taiwan

Nien-yu Tsai